ATPG and DFT — Architecture and Principles
Introduction
Design‑for‑Testability (DFT) and Automatic Test Pattern Generation (ATPG) provide the structural foundation for detecting manufacturing defects, validating logic integrity, and ensuring that digital systems remain observable and controllable during test.
These techniques are essential for production testing, in‑field diagnostics, and safety‑critical applications where fault detection must be measurable, repeatable, and quantifiable.
Why DFT Matters
Modern digital systems contain millions of internal nodes that cannot be directly accessed from I/O pins. Without DFT, most internal faults would be invisible. DFT introduces architectural features that make internal logic testable:
- Controllability — the ability to drive internal nodes to known values
- Observability — the ability to observe internal states at chip outputs
- Fault isolation — identifying where a defect has occurred
- Repeatability — deterministic test behavior across devices and conditions
These properties are essential for both manufacturing test and functional safety.
Core DFT Techniques
DFT relies on a set of architectural mechanisms that expose internal logic for testing:
- Scan chains — converting flip‑flops into a shift register for full internal visibility
- Test points — improving controllability and observability in hard‑to‑reach logic
- Boundary scan (JTAG) — standardized access to pins and internal registers
- Clock control — enabling deterministic capture and shift operations
- Compression logic — reducing test time and pattern volume
These techniques form the backbone of structural testability.
ATPG Fundamentals
ATPG generates deterministic test patterns that target specific fault models. These patterns are applied through scan chains to detect structural defects.
Common fault models include:
- Stuck‑at faults
- Transition faults
- Bridging faults
- Path delay faults
- Open/short defects
ATPG tools analyze the circuit structure to determine the minimum set of patterns required to achieve high fault coverage.
Built‑In Self‑Test (BIST)
BIST brings test generation and response analysis inside the chip, enabling autonomous testing during startup or runtime.
- LBIST — pseudo‑random pattern generation and MISR‑based signature compression
- MBIST — memory‑specific algorithms for SRAM, register files, and embedded memories
- FBIST — functional test sequences executed internally
BIST is essential for systems that require periodic self‑test or in‑field diagnostics.
BIST Execution Modes
- Power‑Up BIST (Startup Tests)
Full LBIST and MBIST sequences executed before the system becomes operational.
These tests validate logic integrity, memory correctness, and structural behavior at boot time, ensuring that the system enters service in a known‑good state. - Online BIST (Periodic or Runtime Tests)
Partial or segmented BIST routines executed during normal operation.
These tests maintain diagnostic coverage without interrupting system functionality, supporting safety requirements for continuous monitoring and fault detection.
Power‑up BIST ensures a safe starting state.
Online BIST ensures continued integrity during operation.
ATPG and Safety
DFT and ATPG directly support functional safety by enabling measurable diagnostic coverage and reliable fault detection.
Key connections include:
- Structural fault coverage — used to quantify diagnostic capability
- LBIST for safety‑critical startup tests
- MBIST for memory integrity validation
- Scan‑based observability for fault isolation
- ATPG patterns for safety validation and fault injection
These mechanisms contribute directly to FMEDA, FIT budgeting, and safety case justification.
DFT Across DexterLab Domains
DFT and ATPG concepts apply to many functional blocks described in DexterLab:
- FIFO and buffering structures
- CDC and synchronization logic
- Line coding and data integrity blocks
- CRC and error detection logic
- PHY interfaces and protocol layers
- Digital I/O and boundary scan
- Processing units and control logic
- Embedded memories and register files
Structural testability is a transversal requirement across the entire architecture.
ATPG/DFT Cluster Pages
These pages extend the ATPG/DFT domain and are part of this cluster:
- DFT Overview
- Scan Architecture
- Scan Chains — Concepts and Safety Implications
- LBIST Architecture
- MBIST Architecture
- Fault Models
- Test Points and Observability
- Boundary Scan (JTAG / IEEE 1149.1)
- ATPG Pattern Generation
- DFT for Safety‑Critical Systems
- DFT and FIT Contribution
