Scan Chains — Concepts and Safety Implications

Introduction

Scan chains transform sequential logic into a shift‑register structure that exposes internal states for structural testing. By converting flip‑flops into scan‑enabled elements, they provide full controllability and observability of internal nodes, enabling deterministic ATPG pattern application and forming the backbone of DFT and LBIST architectures.

Why Scan Chains Matter

Scan chains are essential for structural testability because they provide:

Internal observability — every scan flip‑flop can be shifted out and inspected.
Internal controllability — ATPG can load arbitrary states into the design.
Deterministic capture — controlled transitions for fault detection.
Repeatability — identical behavior across devices and test conditions.
Safety‑critical diagnostic coverage — required for ISO 26262 and similar standards.

Without scan chains, most internal faults would be undetectable.

Core Concepts

Scan Flip‑Flops

Standard flip‑flops augmented with a multiplexer that selects between functional data and scan data.

Scan Enable and Scan Mode

A global control signal (scan_en) switches the design between:

Shift mode — flip‑flops behave as a shift register.
Capture mode — flip‑flops capture functional responses.

Shift, Capture, Update Phases

Structural testing alternates between:

Shift — load ATPG patterns and unload responses.
Capture — apply functional clocks to excite faults.
Update — propagate captured values into the scan chain.

Scan Stitching and Chain Balancing

Flip‑flops are connected into chains. Balancing ensures:

similar chain lengths
predictable test time
uniform compression efficiency

Compression and Decompression Logic

Modern DFT uses:

Decompressors to expand compressed ATPG patterns
Compressors/MISRs to compact responses

This reduces test time and tester memory requirements.

Safety Implications

Scan chains directly support functional safety by enabling:

Fault isolation — precise localization of structural defects.
LBIST execution — pseudo‑random patterns rely on scan infrastructure.
Startup diagnostics — ensuring logic integrity before enabling safety functions.
FMEDA contributions — structural coverage for stuck‑at, transition, and bridging faults.
Deterministic fault injection — validating safety mechanisms.

Scan infrastructure is a mandatory component in safety‑critical SoCs.

Failure Modes and Diagnostics

Typical scan‑related failure modes include:

Broken scan chain — open/short in the shift path prevents pattern propagation.
Stuck scan enable — design locked in shift or capture mode.
Incorrect capture timing — misaligned clocks causing invalid responses.
MISR signature mismatch — LBIST detects unexpected behavior.
Chain imbalance — excessive test time or compression inefficiency.
X‑propagation issues — unknown states corrupting signatures.

Diagnostics rely on: