MBIST Architecture
Introduction
Memory Built‑In Self‑Test (MBIST) provides autonomous, deterministic testing of embedded memories such as SRAMs, register files, and caches. Unlike logic BIST, which targets combinational and sequential logic, MBIST is optimized for memory‑specific fault models and uses algorithmic test sequences known as March tests.
Why MBIST Is Essential
Embedded memories dominate modern SoCs in both area and defect density. MBIST is required because:
- Detects memory‑specific faults that logic ATPG cannot target
- Required for SRAMs, register files, and cache arrays
- Supports both startup and runtime integrity checks
- Contributes to diagnostic coverage for safety‑critical systems
Core Architectural Components
Address Generator
Generates the sequence of memory addresses according to the selected March algorithm (up, down, up/down traversal).
Data Pattern Generator
Produces deterministic data patterns such as all‑0, all‑1, checkerboard, walking 1/0, or algorithm‑specific transitions.
Comparator
Compares read data against expected values and flags mismatches.
Fail Logging
Captures failing addresses, expected/observed data, and algorithm step information.
Redundancy Repair (Optional)
Interfaces with BIRA/BISR to remap defective rows or columns using spare elements.
MBIST Controller
Coordinates algorithm execution, timing, read/write operations, and test completion.
Figure 1 — MBIST Architecture
Diagram showing Address Generator, Data Generator, Comparator, Fail Log, MBIST Controller, and Memory Under Test.
March Algorithms
March tests apply ordered sequences of read/write operations to each memory address. They provide high coverage for stuck‑at, transition, coupling, retention, and disturb faults.
Common algorithms include:
- March C‑
- March C+
- March SS
- March LR
Each algorithm consists of “March elements,” such as:
↑ (r0, w1)— upward traversal, read 0, write 1↓ (r1, w0)— downward traversal, read 1, write 0
Figure 2 —March C‑, C+, LR, and SS Algorithms
Comparison of four common March algorithms used for memory testing. Each algorithm is expressed as a sequence of address directions (A↑, A↓) and read/write operations. March C‑ and C+ differ in the presence of immediate read‑back checks, March LR alternates address directions, and March SS provides extended coverage through longer operation sequences.
Table1 — Comparison of March C‑, C+, LR, and SS Algorithms
| Algorithm | Length | Fault Coverage | Complexity | Notes |
|---|---|---|---|---|
| C- | Short | Good | Low | Industrial baseline |
| C+ | Medium | Very Good | Medium | Adds immediate read‑back |
| LR | Medium | Very Good | Medium | Alternating address directions |
| SS | Long | Very High | High | Safety‑critical applications |
Comparative summary of four March algorithms, highlighting the number of steps, address directions (A↑, A↓), and the sequence of read/write operations. The table emphasizes the structural differences between basic (C‑), enhanced (C+), alternating‑direction (LR), and extended‑coverage (SS) March tests.
Safety and Diagnostic Coverage
MBIST contributes directly to functional safety:
- Detects stuck‑at, transition, coupling, retention, and disturb faults
- Supports periodic memory integrity checks
- Enables power‑up self‑test before memory is used
- Provides diagnostic coverage required for ASIL C/D
Execution Modes
Power‑Up MBIST
Runs at system startup before software accesses the memory.
Online MBIST (Windowed)
Executes during normal operation on memory regions temporarily taken offline.
Background Scrubbing (Optional)
Periodically reads and rewrites memory to detect retention or soft errors.
