Security in PHY Interfaces
Overview
PHY interfaces bridge the digital system with the physical transmission medium. Because they operate at the boundary between analog signaling and digital logic, they are exposed to threats that do not exist at higher protocol layers:
- electrical manipulation
- timing abuse
- symbol‑level spoofing
- analog front‑end tampering
- probing and eavesdropping
Security analysis focuses on ensuring that the PHY behaves correctly even under malicious interference, not just random noise. This includes protecting link initialization, symbol decoding, clock recovery, and configuration registers.
Conceptual Diagram — Where PHY Attacks Occur
Attacks target the analog and digital PHY blocks, often bypassing protocol‑level protections unless mitigations are in place.
Main Security Threats
Signal Spoofing and Tampering
Injecting forged symbols, transitions, or voltage levels to:
- force link renegotiation
- manipulate training sequences
- confuse alignment logic
Electrical Fault Injection
Inducing:
- voltage dips
- short‑to‑battery/ground
- fast transients
to corrupt PHY logic or force resets.
CDR Manipulation
Attacking clock recovery by:
- jitter injection
- missing transitions
- timing abuse
leading to symbol mis‑decoding or link instability.
Line Coding Exploitation
Crafting symbol sequences that stress:
- disparity
- alignment
- decoder thresholds
- comma detection
to desynchronize the link.
Replay and Desynchronization
Replaying valid symbol streams to:
- confuse link state machines
- force renegotiation
- bypass training sequences
Probing and Eavesdropping
Physically accessing differential pairs or single‑ended lines to:
- read data
- inject signals
- alter impedance
Analog Front‑End Attacks
Exploiting:
- receiver sensitivity
- bias circuits
- threshold comparators
to force mis‑detection or false transitions.
PHY Register Manipulation
Malicious software or compromised firmware altering:
- thresholds
- equalization settings
- link modes
- training parameters
Denial of Service
Overwhelming the link with:
- malformed symbols
- excessive transitions
- forced errors
to degrade or block communication.
Mitigation Techniques
Symbol Integrity and Plausibility Checks
- disparity validation
- alignment checks
- illegal symbol detection
- training sequence verification
Electrical Anomaly Detection
Monitoring:
- voltage
- current
- impedance
- line bias
to detect tampering or probing.
CDR Hardening
- jitter tolerance
- lock supervision
- abnormal transition pattern detection
Secure PHY Configuration
- lock configuration registers after initialization
- restrict access to PHY control interfaces
- enforce secure defaults
Redundant Link Supervision
- cross‑checking link status
- monitoring error counters
- validating symbol rates
Replay and Freshness Protection
- sequence counters
- link‑level freshness markers
- protocol‑layer integrity (MACsec, IPsec, TLS)
Shielding and Routing Protection
- controlled impedance routing
- shielding of differential pairs
- minimizing exposure to probing
End‑to‑End Cryptographic Integrity
Even if the PHY is manipulated, higher‑layer cryptography ensures:
- no data forgery
- no unauthorized injection
- no silent corruption
Built‑In Self‑Test (BIST)
Detects:
- analog degradation
- tampering
- abnormal behavior
during operation or startup.
Relationship with Safety
Safety deals with random disturbances:
- noise
- aging
- analog drift
- environmental stress
Security deals with intentional manipulation:
- crafted symbol sequences
- targeted jitter
- malicious probing
- forced errors
Overlap
- Fault injection resembles electrical faults
- Link integrity monitoring helps detect both accidental and malicious anomalies
- Robust CDR and line coding improve resilience to both noise and attacks
