PHY Interfaces — Architecture and Signaling

Introduction

PHY interfaces define how digital data is transformed into physical signals suitable for transmission across copper traces, cables, connectors, or optical/RF media. This page introduces the architectural layers of a PHY and the signaling mechanisms that enable reliable, high‑speed communication.

A PHY typically includes:

• a coding layer (mapping bits to symbols)
• a serialization layer (parallel‑to‑serial conversion)
• a timing layer (clock recovery and alignment)
• an electrical layer (drivers, receivers, termination)
• a link‑management layer (training, negotiation, status reporting)

Understanding these layers provides the foundation for analyzing any modern serial interface.

PHY Architecture Overview

A generic PHY is composed of three major sublayers:

1. PCS — Physical Coding Sublayer

Responsible for symbol mapping, line coding, and framing.

Functions include:

• block coding (8b/10b, 64b/66b, 128b/130b)
• scrambling / descrambling
• running disparity control
• alignment markers
• symbol framing and deskewing

2. PMA — Physical Medium Attachment

Responsible for serialization, deserialization, and timing recovery.

Functions include:

• serializer / deserializer (SERDES)
• bit alignment and lane alignment
• clock and data recovery (CDR)
• elastic buffers for rate adaptation
• equalization (FFE, CTLE, DFE depending on technology)

3. PMD — Physical Medium Dependent

Responsible for the electrical or optical interface to the medium.

Functions include:

• differential drivers and receivers
• termination and impedance matching
• transmit pre‑emphasis / de‑emphasis
• receive equalization
• optical modulation (for fiber PHYs)
• RF front‑end (for wireless PHYs)

Signaling Types

Different PHYs use different signaling schemes depending on speed, medium, and power constraints.

Voltage‑Mode Signaling

Used in lower‑speed or legacy interfaces:

• UART
• CAN / LIN
• MDIO

Characteristics:

• single‑ended or differential
• larger voltage swings
• simpler receivers

Current‑Mode Signaling

Used in high‑speed differential links:

• PCIe
• USB 3.x / USB4
• Ethernet SERDES
• MIPI D‑PHY / C‑PHY
• DisplayPort / HDMI

Characteristics:

• low voltage swing
• high bandwidth
• controlled impedance
• strong EMI performance

Modulated Signaling

Used when higher spectral efficiency is required:

• PAM‑4 (modern Ethernet, PCIe 6.0)
• OFDM (Wi‑Fi, DSL)
• FSK / ASK / PSK (RF PHYs)

Link Initialization and Training

Most PHYs require a startup sequence to establish a stable link.

Typical steps:

• signal detection
• CDR lock acquisition
• equalizer adaptation
• lane alignment
• auto‑negotiation (Ethernet)
• link training (PCIe, USB3, DisplayPort)

Clocking and Synchronization

PHYs rely heavily on timing integrity.

Mechanisms include:

• embedded clock recovery
• PLL/DLL‑based timing
• transition density from line coding
• elastic buffers for rate matching
• phase alignment across lanes

Related Pages

These pages provide foundational concepts used by PHY architectures:

• Electrical Signaling & PHY Interfaces — Overview
• PHY Interfaces — Line Coding and Modulation
• PHY Interfaces — CDR, Jitter, and Timing
• PHY Interfaces — Electrical Characteristics and Diagnostics
• Line Coding — Overview & Families
• Clocking & Synchronization — Overview
• Data Integrity — Overview
• Safety in PHY Interfaces