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Delayed Lockstep

Overview

Delayed lockstep is a fault‑detection technique in which two processing channels execute the same instruction stream with a small, intentional time offset. This temporal diversity reduces the probability that a disturbance affects both channels during the same logical operation, improving robustness against common‑cause faults.

Motivation

In cycle‑by‑cycle lockstep, both cores execute the same instruction in the same clock cycle. A simultaneous disturbance—such as an EMI burst, voltage dip, or radiation strike—may corrupt both cores identically, producing matching wrong outputs that the comparator cannot detect.

By introducing a delay of one or more cycles between the main core and the checker core, the same disturbance affects different instructions, making mismatches detectable.

Architecture Concept

A delayed lockstep system consists of:

  • Main core — executes the instruction stream normally.
  • Checker core — executes the same instructions but with a fixed delay.
  • Comparator — aligns the outputs of the two cores in time and checks for mismatches.
  • Buffering logic — stores the main core’s outputs until the checker core reaches the corresponding instruction.

Figure 1: Delayed Lockstep Timing Diagram

Delayed lockstep timing. The checker core executes the same instruction stream with a fixed cycle offset. A disturbance occurring at a single physical instant affects different logical operations in the two cores, making mismatches detectable and improving robustness against common‑cause faults.

Benefits

  • Improved common‑cause fault detection — temporal diversity prevents identical corruption.
  • Low hardware overhead — similar to standard lockstep, with added buffering.
  • Compatible with existing CPU architectures — requires minimal changes to the execution pipeline.

Limitations

  • Detection latency — faults are detected after the delay interval.
  • Not effective against long‑duration disturbances — if a disturbance persists across multiple cycles, both cores may still be affected.
  • Requires precise alignment logic — comparator and buffering must be tightly synchronized.

Use Cases

  • Automotive microcontrollers
  • Industrial safety controllers
  • Avionics processors
  • Radiation‑tolerant embedded systems

See Also

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