Common‑Cause Faults
Overview
Common‑cause faults occur when two or more redundant channels fail simultaneously due to a shared disturbance or dependency. Unlike independent random faults, common‑cause faults can defeat redundancy mechanisms such as dual‑core lockstep or TMR if not properly mitigated.
These faults arise from shared physical resources, environmental conditions, or design dependencies that cause multiple channels to behave incorrectly in the same way.
Sources of Common‑Cause Faults
- Shared clock trees — a glitch or jitter event affects all synchronous domains.
- Shared power domains — voltage dips, brownouts, or supply noise propagate to all channels.
- Shared instruction or data fetch paths — corrupted memory or bus transactions feed identical wrong data to all channels.
- Environmental disturbances — EMI bursts, radiation strikes, thermal hotspots.
- Design or implementation dependencies — identical logic, identical placement, or identical routing.
Impact on Redundant Architectures
Dual‑Core Lockstep (DMR)
If both cores receive the same wrong input or are disturbed in the same cycle, they may produce identical wrong outputs. The comparator cannot detect the mismatch, resulting in an undetected fault.
Delayed Lockstep
Temporal diversity reduces the probability of simultaneous corruption. A disturbance hitting both cores at the same physical time affects different instructions, making mismatches detectable.
Triple‑Modular Redundancy (TMR)
TMR masks single‑channel faults, but common‑cause faults can corrupt two or all three channels, defeating the majority voter.
Mitigation Techniques
Spatial diversity
Physically separate redundant channels to reduce the chance of a single disturbance affecting all of them.
Temporal diversity
Introduce timing offsets (e.g., delayed lockstep) so that a disturbance does not align with the same logical operation.
Power and clock partitioning
Use independent regulators, clock sources, or isolation techniques to avoid shared failure domains.
Data and instruction diversity
Use mirrored memory banks, ECC‑protected buses, or diversified fetch paths.
