Security in Reset
Overview
Reset logic defines the initial conditions of the system and governs how subsystems return to a known state. Because reset affects every register, state machine, and control path, it is a powerful target for attackers.
Manipulating reset signals can:
- desynchronize modules
- bypass security checks
- force illegal states
- corrupt initialization sequences
- disrupt communication
- trigger partial or inconsistent resets
Security analysis focuses on protecting reset paths from tampering, ensuring clean and authenticated reset sources, and detecting abnormal reset behavior.
Conceptual Diagram — Where Reset Attacks Occur
Reset attacks can target any of these layers, often with subtle timing or electrical manipulation.
Main Security Threats
External Reset Tampering
Manipulating external reset pins via:
- noise
- forced pulses
- electrical injection
- probing or shorting
to force unintended resets.
Glitch‑Based Reset Attacks
Injecting:
- short pulses
- malformed reset edges
- partial resets
to corrupt internal states or bypass initialization.
Reset Desynchronization
Forcing different modules to exit reset at different times, causing:
- inconsistent states
- partial initialization
- bypass of security checks
Reset Domain Crossing Abuse
Exploiting metastability or timing faults during reset release across clock domains.
Unauthorized Reset Triggering
Malicious software or compromised peripherals forcing resets to:
- bypass authentication
- restart secure boot
- clear volatile protections
Brown‑Out Exploitation
Manipulating supply voltage to trigger:
- partial resets
- undefined states
- reset loops
Reset Controller Manipulation
Altering:
- configuration registers
- mode bits
- reset routing
to weaken reset behavior.
Denial of Service
Repeatedly forcing resets to:
- block normal operation
- disrupt communication
- degrade system availability
State Machine Corruption on Reset Release
Manipulating timing to force:
- illegal states
- skipped initialization steps
- inconsistent control logic
Mitigation Techniques
Secure Reset Sources
- validate external reset inputs
- filter noise and malicious pulses
- enforce minimum pulse width
Reset Authentication
Require cryptographic or protocol‑level authorization for software‑triggered resets.
Glitch Filtering and Stretching
Ensure:
- minimum reset duration
- rejection of malformed pulses
- clean reset edges
Synchronized Reset Release
Align reset deassertion with clock domains to prevent metastability.
Reset Supervision
Monitor:
- reset frequency
- duration
- patterns
to detect abnormal behavior.
Brown‑Out Protection
Use:
- undervoltage detectors
- controlled reset sequences
- power‑good monitors
Configuration Locking
Protect reset controller registers and mode bits after initialization.
Redundant Reset Paths
Use dual or monitored reset sources for high‑integrity systems.
Built‑In Self‑Test
Validate:
- reset distribution
- controller logic
- domain synchronization
to detect tampering or degradation.
Relationship with Safety
Safety deals with random reset faults:
- noise
- brown‑out
- timing issues
- analog degradation
Security deals with intentional manipulation:
- crafted glitches
- forced partial resets
- malicious reset loops
Overlap
- Fault injection resembles brown‑out or glitch faults
- Clean reset release and robust filtering help both domains
- Reset supervision improves resilience to both accidental and malicious resets
