Reset — Asynchronous vs Synchronous Strategies
Overview
Reset strategies determine how reset signals are asserted and deasserted relative to the system clock. The choice between asynchronous and synchronous reset has deep implications for safety, timing integrity, metastability, and deterministic initialization. In safety‑critical systems, reset behavior must be predictable, glitch‑free, and aligned with the clocking architecture.
This page explains the safety‑relevant differences between asynchronous and synchronous reset, their advantages, risks, and recommended usage patterns.
Asynchronous Reset
Asynchronous reset is asserted independently of the clock. It immediately forces registers and logic into a known state.
Advantages
- Immediate reaction to faults (e.g., brown‑out, watchdog expiration).
- Works even when the clock is unstable or stopped.
- Simple implementation for global reset.
Safety Risks
- Glitches: noise or transients may cause unintended resets.
- Metastability on release: if deasserted near a clock edge.
- Reset domain crossing (RDC): asynchronous reset entering a different clock domain.
- Partial reset: if reset pulse width is too short.
Mitigation
- Synchronize reset deassertion to the destination clock.
- Use glitch filters on external reset inputs.
- Stretch reset pulses to guarantee minimum width.
- Validate reset integrity through monitoring.
Synchronous Reset
Synchronous reset is asserted and deasserted only on clock edges.
Advantages
- Fully deterministic timing.
- No metastability on release.
- Reset behavior is aligned with the clock domain.
- Easier RDC management.
Safety Risks
- Clock dependency: reset cannot function if the clock is unstable or stopped.
- Longer reaction time: reset takes effect only on the next clock edge.
- Clock gating interaction: gated clocks may block reset propagation.
Mitigation
- Ensure clock availability during reset.
- Use dedicated reset‑capable clock paths.
- Combine synchronous release with asynchronous assertion.
Hybrid Reset Strategies
Many safety‑critical systems use a hybrid approach:
Asynchronous Assertion + Synchronous Release
- Immediate reaction to faults.
- Safe, deterministic exit from reset.
- Avoids metastability and partial initialization.
Domain‑Specific Reset Strategies
- Asynchronous reset for global and power‑related events.
- Synchronous reset for CPU, peripherals, and tightly timed logic.
This hybrid model is the most common in ASIL‑capable designs.
Reset Domain Crossing (RDC)
Reset signals crossing clock domains must be treated with the same rigor as CDC.
RDC Risks
- Metastability on reset release.
- Illegal FSM states.
- Partial initialization.
RDC Mitigation
- Synchronize reset deassertion per domain.
- Use reset synchronizers.
- Validate RDC paths during design and verification.
Safety Recommendations
- Use asynchronous assertion for fault‑driven resets.
- Use synchronous release for deterministic initialization.
- Filter and debounce external reset inputs.
- Guarantee minimum reset pulse width.
- Validate reset behavior across voltage, temperature, and frequency.
- Include reset logic in BIST and ATPG.
