Framing & Alignment — Architecture & Practical Considerations

Overview

Framing and alignment define how a receiver identifies symbol boundaries, block boundaries, and protocol‑level structures within a serial data stream. Modern high‑speed links rely on explicit markers, sync headers, comma patterns, and correlator‑based detection to achieve fast lock acquisition, robust loss‑of‑lock detection, and reliable multi‑lane synchronization.
These mechanisms are essential for block‑coded systems such as 8b/10b, 64b/66b, and 128b/130b, as well as for multi‑lane protocols that require lane bonding and deskew.

1. Why Framing and Alignment Matter

High‑speed serial receivers must determine where each symbol or block begins. Without explicit framing:

• block boundaries drift over time
• CDR cannot maintain stable sampling
• control symbols cannot be decoded
• multi‑lane links cannot be deskewed
• error detection becomes unreliable

Framing and alignment ensure:

• deterministic block boundaries
• fast lock acquisition
• robust loss‑of‑lock detection
• correct interpretation of control/data blocks
• reliable multi‑lane operation

2. Alignment Mechanisms Across Line Codes

Comma Detection (8b/10b)

8b/10b uses special K‑characters (e.g., K28.5) with unique bit patterns that cannot appear in normal data.
The receiver performs:

• sliding window search
• comma pattern detection
• alignment to 10‑bit boundaries

Comma detection provides extremely fast lock and strong error detection.

Sync Headers (64b/66b and 128b/130b)

Block‑coded systems use a 2‑bit sync header:

• 01 → data block
• 10 → control block
• 00 / 11 → invalid

The receiver:

• scans for valid headers
• aligns to 66‑bit or 130‑bit boundaries
• monitors invalid headers for loss‑of‑lock

Sync headers are unscrambled to guarantee detectability.

Alignment Markers (Ethernet, PCIe, USB4)

Multi‑lane protocols insert periodic alignment markers:

• unique multi‑byte patterns
• scrambled or unscrambled depending on protocol
• used for lane deskew
• used for lane ordering

Examples:

• Ethernet AM (Alignment Marker)
• PCIe SKP ordered sets
• USB4 TS1/TS2 training sequences

Correlator‑Based Alignment

Some protocols use correlators to detect:

• training sequences
• preambles
• frame headers
• alignment words

Correlation provides robustness against noise and jitter.

3. Receiver Architecture for Alignment

Sliding Window Search

The receiver examines the incoming bitstream in a sliding window:

• 10 bits for 8b/10b
• 66 bits for 64b/66b
• 130 bits for 128b/130b

It checks for:

• comma patterns
• sync headers
• alignment markers
• correlation peaks

Lock / Loss‑of‑Lock State Machine

Receivers implement a state machine:

• Acquire — search for alignment
• Verify — confirm multiple consecutive valid markers
• Lock — aligned
• Monitor — check for invalid markers
• Loss‑of‑Lock — re‑enter search mode

This ensures stability even under noise and jitter.

Multi‑Lane Deskew

Protocols with multiple lanes require:

• per‑lane alignment
• deskew FIFOs
• periodic alignment markers
• lane ordering logic

Deskew ensures that all lanes deliver aligned blocks to the PCS.

4. Practical Considerations

Transition Density

Alignment relies on:

• transitions for CDR
• unscrambled headers
• periodic markers

Low transition density increases lock time.

Error Detection

Alignment mechanisms provide structural error detection:

• invalid sync headers
• missing alignment markers
• incorrect comma patterns
• correlation failures

These errors often trigger loss‑of‑lock.

Scrambling Interaction

Scrambling improves spectral properties but:

• must not affect sync headers
• must not affect comma patterns
• may affect alignment markers depending on protocol

Protocols define which fields are scrambled and which are not.

Latency and Overhead

Alignment mechanisms introduce:

• minimal overhead (headers, markers)
• small latency (deskew FIFOs)
• deterministic behavior

The trade‑off is robustness vs. bandwidth efficiency.

5. Use Cases Across Protocols

8b/10b Systems

• comma detection
• K‑characters
• deterministic alignment

64b/66b Systems

• sync headers
• alignment markers for multi‑lane Ethernet

128b/130b Systems

• sync headers
• SKP ordered sets (PCIe)
• training sequences (USB4, Thunderbolt)

JESD204B/C

• frame alignment
• multiframe alignment
• lane alignment

SATA / SAS

• alignment primitives
• OOB signaling

6. Related Pages

• Line Coding — Overview & Families
• 8b/10b — Overview, Tables & Implementation Notes
• 64b/66b Encoding — Architecture & Fundamentals
• 128b/130b Encoding — Architecture & Fundamentals
• Scrambling — Architecture, Modes & Implementation Notes
• Correlator — Architecture & Fundamentals

Summary

Framing and alignment define how receivers identify block boundaries, detect control symbols, and maintain synchronization across lanes and protocol layers. Techniques such as comma detection, sync headers, alignment markers, and correlator‑based detection provide fast lock acquisition, robust error detection, and reliable multi‑lane operation. These mechanisms are essential for modern block‑coded systems such as 8b/10b, 64b/66b, and 128b/130b, and form the foundation of high‑speed serial protocols including Ethernet, PCIe, USB4, Thunderbolt, and JESD204B/C.