64b/66b Encoding — Architecture & Fundamentals
Overview
This page describes the architecture, encoding rules, scrambling mechanisms, and alignment techniques used in 64b/66b systems.
64b/66b is a line coding scheme used in high‑speed serial communication systems to efficiently transport data while maintaining sufficient transition density for clock recovery. It replaces 8b/10b by dramatically reducing overhead (from 25% to 3.125%) and improving spectral properties through scrambling.
Each block consists of a 2‑bit sync header followed by a 64‑bit payload. The header identifies the block type, while the payload is scrambled to ensure DC balance and spectral whitening.
64b/66b is used in 10G Ethernet, OTN, and several multi‑gigabit serial standards.
Block Structure
A 64b/66b block contains:
- 2‑bit sync header (unscrambled)
- 64‑bit scrambled payload
Sync Header Table
| Sync Header | Meaning | Description |
|---|---|---|
| 01 | Data Block | Payload contains only data bits |
| 10 | Control Block | Payload contains control information |
| 00 / 11 | Invalid | Used for error detection |
The sync header is intentionally not scrambled, enabling reliable block alignment and fast synchronization.
Scrambling Architecture
The 64‑bit payload is scrambled using a self‑synchronous scrambler based on the polynomial:
Scrambler Properties
- Ensures DC balance
- Eliminates long runs of identical bits
- Reduces EMI and spectral peaks
- No explicit seed exchange required
- Descrambler locks automatically after a few bits
Scrambling is essential because the 64‑bit payload alone does not guarantee transition density.
Encoder Architecture
The encoder performs three main operations:
- Determine block type (data or control)
- Insert the appropriate sync header
- Scramble the 64‑bit payload
Encoder Flow
| Step | Operation | Description |
|---|---|---|
| 1 | Block Classification | Identify whether the 64‑bit payload is data or control |
| 2 | Sync Header Insertion | Add 01 (data) or 10 (control) |
| 3 | Payload Scrambling | Apply the self‑synchronous scrambler |
| 4 | Block Output | Produce the final 66‑bit block |
Encoder Output Format
Decoder Architecture
The decoder reverses the encoding process:
- Detect sync header
- Classify block type
- Descramble the payload
- Deliver 64‑bit data or control information
Decoder Flow
Descrambler
| Step | Operation | Description |
|---|---|---|
| 1 | Sync Header Detection | Identify 01 (data) or 10 (control) |
| 2 | Block Alignment | Use sync header to maintain 66‑bit alignment |
| 3 | Payload Descrambling | Apply the same polynomial as the scrambler |
| 4 | Output Delivery | Provide 64‑bit data or control payload |
The descrambler uses the same polynomial:
Because the scrambler is self‑synchronous, the descrambler automatically locks after a short transient.
Advantages
- Very low overhead (3.125%)
- Excellent spectral properties
- High transition density for clock recovery
- Simple block structure
- Scalable to multi‑gigabit speeds
- Compatible with multi‑lane architectures
Limitations
- Burst error propagation due to scrambling
- Descrambler requires a short lock time
- Sync header is only 2 bits (vulnerable to noise)
- More complex than 8b/10b in alignment and error detection
Use Cases
64b/66b is used in:
- 10G Ethernet (IEEE 802.3ae)
- OTN (Optical Transport Network)
- High‑speed backplane links
- Some Fibre Channel variants
- Proprietary SerDes protocols
Implementation Notes
- Sync header must remain unscrambled
- Scrambler and descrambler must use the same polynomial
- Block alignment relies on detecting the sync header pattern
- Error detection often uses CRC or FEC at higher layers
- Multi‑lane systems require alignment markers
- Hardware implementations pipeline the scrambler for timing closure
Related Pages
- Line Coding — Overview & Families
- NRZ / NRZI — Coding
- MLT‑3 Coding
- Scrambling — Architecture, Modes & Implementation Notes
- 8b/10b — Overview, Tables & Implementation Notes
- 128b/130b Encoding — Architecture & Fundamentals
- PAM4 Signaling — Architecture & Challenges
- Manchester Coding
Summary
- 64b/66b reduces overhead to 3.125%, replacing 8b/10b in high‑speed serial links.
- Each block contains a 2‑bit sync header and a 64‑bit scrambled payload.
- The sync header identifies data or control blocks and remains unscrambled for alignment.
- The payload is scrambled using a self‑synchronous scrambler based on the polynomial x^{58}+x^{39}+1.
- The encoder inserts the sync header and scrambles the payload; the decoder detects the header, aligns blocks, and descrambles.
- 64b/66b is used in 10G Ethernet, OTN, and other multi‑gigabit communication standards.
- It offers excellent spectral properties and transition density, with the trade‑off of error propagation due to scrambling.
64b/66b is the foundation of modern high‑speed serial communication and the natural evolution of 8b/10b for multi‑gigabit systems.
