PAM4 Signaling — Architecture & Challenges

Introduction

PAM4 (Pulse‑Amplitude Modulation with 4 levels) is a multi‑level signaling scheme that transmits 2 bits per symbol by using four distinct voltage levels instead of the two used in NRZ/PAM2.
By doubling the number of bits per unit interval (UI), PAM4 enables extremely high data rates without doubling the Nyquist frequency, making it essential for modern high‑speed interfaces such as PCIe Gen6, 100G/200G/400G Ethernet, and GDDR6X.

However, PAM4 introduces significant challenges in noise margin, jitter tolerance, equalization, and error correction, requiring advanced SERDES architectures.

Why PAM4 Exists

Scaling Limitations of NRZ

As NRZ approaches 25–32 Gbps:

channel loss becomes extreme
equalization complexity grows
jitter tolerance collapses
power consumption increases

PAM4 solves this by:

transmitting 2 bits per UI
halving the required Nyquist frequency
enabling 50–128 Gbps operation on existing channels

PAM4 Benefits

doubles data rate without doubling bandwidth
reduces channel requirements
enables long‑reach high‑speed links
compatible with existing PCB materials and connectors

PAM4 Signaling Basics

Voltage Levels

PAM4 uses four amplitude levels:

Level 0
Level 1
Level 2
Level 3

Each level encodes 2 bits:

Eye Diagram

PAM4 produces three eyes instead of one:

upper eye
middle eye
lower eye

Each eye is one‑third the height of an NRZ eye.

Consequences

reduced noise margin
increased sensitivity to jitter
higher BER without FEC
more complex equalization

PAM4 Transmitter Architecture

TX Components

multi‑level DAC or weighted driver
FFE (pre‑cursor and post‑cursor taps)
swing control
impedance calibration

TX Challenges

linearity of output driver
accurate level spacing
distortion from FFE taps
increased power consumption

TX Equalization

FFE is essential to compensate for:

precursor ISI
post‑cursor ISI
channel high‑frequency loss

PAM4 Receiver Architecture

RX Components

CTLE for analog HF boost
multi‑threshold slicers (3 thresholds)
DFE with multiple taps
CDR with multi‑level phase detection
deserializer

RX Challenges

reduced eye height → harder slicing
ISI affects all three eyes differently
DFE must handle multi‑level decisions
CDR must track transitions with lower amplitude

Equalization Requirements

PAM4 requires:

stronger CTLE
deeper DFE
coordinated TX/RX equalization
adaptive tuning during link training

Jitter and Noise in PAM4

Noise Margin

NRZ eye height = 100%
PAM4 eye height ≈ 33%

Noise sources:

thermal noise
crosstalk
supply noise
ISI
quantization noise

Jitter Sensitivity

PAM4 is more sensitive to:

random jitter
deterministic jitter
ISI‑induced jitter
CDR phase noise

Impact on BER

PAM4 BER is typically 10× to 100× worse than NRZ without FEC.

Forward Error Correction (FEC)

Why FEC Is Mandatory

Due to reduced noise margin, PAM4 requires FEC to achieve acceptable BER.

Common FEC Schemes

Reed‑Solomon (RS‑FEC)
LDPC (Low‑Density Parity Check)
BCH codes

FEC Trade‑offs

adds latency
increases power
requires additional bandwidth

Protocols such as Ethernet and PCIe Gen6 mandate FEC.

Link Training for PAM4

Purpose

Adaptive tuning is required to:

optimize TX FFE taps
adjust RX CTLE gain
tune DFE coefficients
calibrate slicer thresholds
stabilize CDR

Protocol Examples

PCIe Gen6
100G/200G/400G Ethernet
DisplayPort UHBR
GDDR6X

Training ensures interoperability across channels.

PAM4 vs NRZ Comparison

Feature	NRZ (PAM2)	PAM4
Bits per symbol	1	2
Eye count	1	3
Eye height	100%	~33%
Noise margin	High	Low
Equalization	Moderate	Heavy
CDR complexity	Moderate	High
FEC required	Optional	Mandatory
Power	Lower	Higher
Data rate scaling	Limited	Excellent

Practical Considerations

Power Consumption

PAM4 increases power due to:

multi‑level drivers
deeper DFE
stronger CTLE
FEC processing

Linearity

TX driver linearity is critical for accurate level spacing.

Crosstalk

PAM4 is more sensitive to crosstalk due to reduced eye height.

Channel Requirements

Channels must support:

low return loss
controlled impedance
minimal reflections

SERDES — Architecture & Fundamentals
Overview of SERDES building blocks and system behavior.
TX Datapath — Pre‑Emphasis, Equalization & Serialization
TX‑side equalization and waveform shaping.
RX Datapath — CTLE, DFE, CDR & Sampling
Receiver equalization and sampling architecture.
Equalization — CTLE / DFE / FFE
Equalization techniques for high‑speed channels.
CDR — Architecture & Loop Dynamics
Timing recovery mechanisms and jitter tolerance.
Channel Modeling — S‑Parameters, ISI & Eye Diagrams
Modeling and analysis of high‑speed channels.

Summary

PAM4 doubles data rate without increasing Nyquist frequency, enabling 50–128 Gbps operation on existing channels. However, it introduces reduced noise margin, increased jitter sensitivity, and higher equalization complexity.
Modern SERDES systems rely on advanced CTLE, DFE, FFE, multi‑level CDR, and mandatory FEC to achieve reliable PAM4 operation across diverse channels and protocols.

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