SERDES — Architecture & Fundamentals
Introduction
Serializer/Deserializer (SERDES) architectures enable high‑speed serial communication by converting wide parallel datapaths into narrow, multi‑gigabit serial lanes and vice versa. They form the physical backbone of modern interfaces such as PCIe, USB4, Ethernet, DisplayPort, and JESD204, where bandwidth, signal integrity, and power efficiency are critical.
A SERDES link integrates analog and digital blocks—TX equalization, RX equalization, CDR, link training, and channel adaptation—to overcome attenuation, ISI, jitter, and crosstalk across copper traces, backplanes, cables, or optical channels.
Core Concepts
Serialization and Deserialization
A SERDES converts between:
- parallel data (e.g., 16–64 bits at moderate frequency)
- serial data (1–4 differential lanes at multi‑GHz rates)
Serialization reduces pin count, routing complexity, and skew, enabling long‑reach, high‑bandwidth communication.
Differential Signaling
SERDES links use differential pairs to:
- reduce EMI
- improve noise immunity
- support high‑frequency operation
- maintain signal integrity over lossy channels
Channel Impairments
High‑speed channels introduce:
- frequency‑dependent attenuation
- reflections and impedance discontinuities
- inter‑symbol interference (ISI)
- crosstalk
- jitter accumulation
SERDES architectures compensate for these impairments through equalization and adaptive tuning.
SERDES Architecture Overview
A complete SERDES link consists of:
Transmitter (TX)
- parallel‑to‑serial conversion
- pre‑emphasis / de‑emphasis
- feed‑forward equalization (FFE)
- output driver and swing control
- impedance calibration
TX equalization shapes the signal to counteract channel loss.
Receiver (RX)
- continuous‑time linear equalizer (CTLE)
- decision feedback equalizer (DFE)
- sampler / slicer
- deserializer
- offset and gain calibration
RX equalization restores eye opening and mitigates ISI.
Clock and Data Recovery (CDR)
- extracts timing from incoming data
- aligns sampling phase
- tracks jitter and frequency offsets
CDR is essential for bit‑error performance.
Link Training
- adaptive tuning of TX/RX equalization
- protocol‑specific training sequences
- dynamic optimization of channel parameters
Used in PCIe, USB4, DisplayPort, and Ethernet KR/KR4.
Equalization Fundamentals
CTLE (Continuous‑Time Linear Equalizer)
- analog high‑frequency boost
- compensates channel low‑pass behavior
- first stage of RX equalization
FFE (Feed‑Forward Equalizer)
- TX‑side pre‑emphasis
- boosts transitions
- combats precursor ISI
DFE (Decision Feedback Equalizer)
- RX‑side ISI cancellation
- subtracts post‑cursor ISI based on previous decisions
- critical for PAM4 links
Equalization is mandatory for multi‑gigabit operation.
CDR Fundamentals
Purpose
CDR aligns sampling instants with data transitions, compensating for:
- jitter
- frequency offsets
- channel distortion
Techniques
- bang‑bang CDR
- linear CDR
- phase interpolators
- PLL/DLL‑based loops
- oversampling architectures
CDR performance directly impacts BER and eye opening.
SERDES Signaling Modes
NRZ (PAM2)
- 2‑level signaling
- used up to ~32 Gbps
- simpler equalization
PAM4
- 4‑level signaling
- doubles data rate at same Nyquist frequency
- requires heavy equalization
- used in PCIe Gen6, 100G/200G/400G Ethernet
PAM4 increases throughput but reduces noise margin.
Channel Modeling and Link Budget
Channel Characterization
- S‑parameters
- impulse response
- insertion loss
- return loss
- crosstalk
Analysis Tools
- eye diagrams
- bathtub curves
- jitter decomposition
- ISI analysis
Link Budget
Defines:
- TX swing
- equalization gain
- jitter tolerance
- BER targets
A robust link budget ensures interoperability and compliance.
Integration with Protocols
SERDES blocks interface with protocol layers such as:
- PCIe PHY
- USB4/Thunderbolt PHY
- Ethernet PCS/PMA
- DisplayPort AUX and main link
- JESD204B/C transport layer
Each protocol defines:
- training sequences
- equalization presets
- lane bonding and deskew
- scrambling and encoding
Practical Considerations
Power Efficiency
High‑speed SERDES consume significant power due to:
- analog equalizers
- CDR loops
- high‑speed drivers
Techniques such as adaptive equalization and low‑swing signaling reduce power.
Jitter Management
Jitter sources include:
- PLL phase noise
- supply noise
- crosstalk
- ISI
CDR and equalization mitigate jitter accumulation.
Multi‑Lane Architectures
High‑bandwidth links use:
- lane bonding
- deskew FIFOs
- alignment markers
Ensuring lane alignment is critical for multi‑lane protocols.
Related Pages
- TX Datapath — Pre‑Emphasis, Equalization & Serialization
Signal shaping and serialization techniques used in modern transmitters. - RX Datapath — CTLE, DFE, CDR & Sampling
Receiver equalization and clock recovery architectures. - CDR — Architecture & Loop Dynamics
Timing recovery mechanisms and jitter tolerance. - Equalization — CTLE / DFE / FFE
Equalization techniques for high‑speed channels. - PAM4 Signaling — Architecture & Challenges
4‑level signaling used in PCIe Gen6 and 100G Ethernet. - Link Training — Architecture & Protocol Examples
Adaptive tuning of equalization parameters. - Channel Modeling — S‑Parameters, ISI & Eye Diagrams
Modeling and analysis of high‑speed channels.
Summary
SERDES architectures enable high‑speed serial communication by combining serialization, equalization, clock recovery, and adaptive link training. Modern interfaces rely on sophisticated TX/RX datapaths, PAM4 signaling, and advanced CDR loops to overcome channel impairments and achieve multi‑gigabit performance.
This page provides the architectural foundation for the SERDES & High‑Speed Interfaces domain and prepares the ground for the detailed pages that follow.
