CDR — Architecture & Loop Dynamics

Introduction

Clock and Data Recovery (CDR) is one of the most critical blocks in any SERDES receiver. Its role is to extract timing information from the incoming data stream and align the sampling clock to the center of the eye, despite jitter, ISI, channel loss, and frequency offsets.
A well‑designed CDR ensures low bit‑error rate (BER), stable sampling, and robust operation across a wide range of channels and signaling modes (NRZ/PAM4).

Modern CDRs combine analog and digital techniques, including phase detectors, loop filters, phase interpolators, and adaptive control loops.

Core Concepts

Why CDR Is Needed

High‑speed serial links do not transmit a separate clock.
Instead, the receiver must recover timing from data transitions.

Challenges:

• jitter accumulation
• ISI‑induced timing distortion
• frequency offset between TX and RX clocks
• channel attenuation and reflections

Without CDR, the sampler would drift away from the eye center, causing rapid BER degradation.

CDR Goals

• align sampling phase to the eye center
• track jitter and frequency drift
• maintain lock under channel impairments
• minimize sampling error

CDR Architecture Overview

A typical CDR includes:

1. Phase Detector (PD)

Compares data transitions with the sampling clock to generate a phase error signal.

Types:

• bang‑bang (Alexander)
• linear (proportional)
• multi‑level (for PAM4)

2. Loop Filter

Shapes the phase‑error signal and determines loop dynamics.

Functions:

• bandwidth control
• jitter filtering
• stability management

3. Phase Interpolator (PI) or VCO

Adjusts the sampling phase based on loop‑filter output.

• PI for digital CDRs
• VCO/PLL for analog CDRs

4. Sampler / Slicer

Samples the equalized signal at the recovered clock phase.

5. Lock Detector

Determines whether the CDR is locked to the data stream.

Phase Detectors

Bang‑Bang Phase Detector (Alexander)

• outputs only “early” or “late”
• simple and robust
• widely used in NRZ links
• nonlinear behavior → requires careful loop design

Linear Phase Detector

• outputs proportional phase error
• better jitter performance
• used in high‑end CDRs and PAM4 receivers

PAM4 Phase Detection

Requires multi‑threshold detection:

• three slicers
• multiple transition types
• more complex timing extraction

Loop Dynamics

Loop Bandwidth

Determines how quickly the CDR reacts to phase changes.

Trade‑offs:

• high bandwidth → tracks jitter but passes noise
• low bandwidth → filters noise but reacts slowly

Jitter Transfer Function

Defines how input jitter propagates to sampling clock.

Jitter Tolerance

Defines how much jitter the CDR can handle without losing lock.

Jitter Generation

Defines how much jitter the CDR itself introduces.

Stability

Loop stability depends on:

• loop filter design
• PD characteristics
• PI/VCO gain
• channel conditions

CDR Techniques

1. PLL‑Based CDR

• uses VCO
• continuous‑time loop
• good jitter filtering
• used in long‑reach links

2. DLL‑Based CDR

• uses delay lines
• stable and low jitter
• limited frequency range

3. Phase‑Interpolator CDR (PI‑CDR)

• fully digital
• used in modern SERDES
• excellent integration and power efficiency

4. Oversampling CDR

• samples data multiple times per UI
• digital logic selects optimal sampling point
• robust but power‑hungry

CDR in PAM4 Systems

PAM4 introduces:

• reduced eye height
• increased ISI
• more jitter sensitivity
• multi‑level transitions

CDR must:

• use multi‑level phase detection
• integrate tightly with DFE
• compensate for eye asymmetry
• support adaptive timing loops

PAM4 CDRs are significantly more complex than NRZ CDRs.

Interaction with Equalization

CDR and equalization are tightly coupled.

CTLE → improves eye opening before CDR

DFE → reduces ISI that distorts timing

FFE → shapes transitions for better timing extraction

Poor equalization → poor CDR lock → high BER.

Practical Considerations

Lock Time

CDR must lock quickly during:

• link initialization
• lane training
• power‑state transitions

Frequency Offset

CDR must track small differences between TX and RX clocks.

Power Consumption

CDR is one of the most power‑hungry blocks in the RX.

Multi‑Lane Systems

Each lane has its own CDR:

• lane‑to‑lane skew must be corrected
• deskew FIFOs align parallel data

Related Pages

• SERDES — Architecture & Fundamentals
  High‑level overview of SERDES building blocks.
• RX Datapath — CTLE, DFE, CDR & Sampling
  Receiver equalization and sampling architecture.
• Equalization — CTLE / DFE / FFE
  Equalization techniques for high‑speed channels.
• PAM4 Signaling — Architecture & Challenges
  4‑level signaling used in PCIe Gen6 and 100G Ethernet.
• Link Training — Architecture & Protocol Examples
  Adaptive tuning of equalization and CDR parameters.
• Channel Modeling — S‑Parameters, ISI & Eye Diagrams
  Modeling and analysis of high‑speed channels.

Summary

CDR is responsible for extracting timing from the incoming data stream and aligning the sampling clock to the eye center. It compensates for jitter, frequency offsets, and ISI, ensuring reliable operation in multi‑gigabit SERDES links.
Modern CDRs use advanced phase detectors, loop filters, and phase interpolators to achieve robust lock, low jitter, and high BER performance across NRZ and PAM4 systems.