128b/130b Encoding — Architecture & Fundamentals
Overview
This page describes the architecture, encoding rules, scrambling mechanisms, and alignment techniques used in 128b/130b systems.
128b/130b is a high‑efficiency line coding scheme used in modern multi‑gigabit serial communication systems. It extends the principles of 64b/66b by increasing the payload size to 128 bits while keeping the sync header at 2 bits, reducing overhead to just 1.54%.
The encoding uses a 2‑bit sync header to identify block type and applies a self‑synchronous scrambler to the 128‑bit payload. This ensures DC balance, spectral whitening, and sufficient transition density for clock recovery.
128b/130b is widely used in PCI Express (Gen3 and above), USB4, Thunderbolt, and high‑speed Ethernet variants.
Block Structure
A 128b/130b block contains:
- 2‑bit sync header (unscrambled)
- 128‑bit scrambled payload
Sync Header Table
| Sync Header | Meaning | Description |
|---|---|---|
| 01 | Data Block | Payload contains data bits |
| 10 | Control Block | Payload contains control information |
| 00 / 11 | Invalid | Unused for error detection |
The sync header remains unscrambled to support reliable block alignment.
Scrambling Architecture
The 128‑bit payload is scrambled using the same self‑synchronous scrambler used in 64b/66b, based on the polynomial:
Scrambler Characteristics
- Ensures DC balance
- Eliminates long runs of identical bits
- Reduces EMI and spectral peaks
- No explicit seed exchange required
- Descrambler locks automatically after a short transient
The scrambler is essential because the 128‑bit payload alone does not guarantee transition density.
Encoder Architecture
The encoder performs:
- Block classification (data or control)
- Sync header insertion
- Payload scrambling
- Block output
Encoder Flow
| Step | Operation | Description |
|---|---|---|
| 1 | Block Classification | Identify whether the 128‑bit payload is data or control |
| 2 | Sync Header Insertion | Add 01 (data) or 10 (control) |
| 3 | Payload Scrambling | Apply the self‑synchronous scrambler |
| 4 | Block Output | Produce the final 130‑bit block |
Encoder Output Format
Decoder Architecture
The decoder reverses the encoding process:
- Detect sync header
- Classify block type
- Descramble the payload
- Deliver 128‑bit data or control information
Decoder Flow
| Step | Operation | Description |
|---|---|---|
| 1 | Sync Header Detection | Identify 01 (data) or 10 (control) |
| 2 | Block Alignment | Use sync header to maintain 130‑bit alignment |
| 3 | Payload Descrambling | Apply the same polynomial as the scrambler |
| 4 | Output Delivery | Provide 128‑bit data or control payload |
Descrambler
Uses the same polynomial:
The descrambler automatically locks after a short transient.
Advantages
- Extremely low overhead (1.54%)
- Excellent spectral properties
- High transition density for clock recovery
- Scales efficiently to very high data rates
- Compatible with multi‑lane architectures
- Reuses the same scrambler as 64b/66b
Limitations
- Burst error propagation due to scrambling
- Descrambler requires a short lock time
- Sync header is only 2 bits (sensitive to noise)
- More complex alignment and error detection than 8b/10b
Use Cases
128b/130b is used in:
- PCI Express Gen3, Gen4, Gen5, Gen6
- USB4
- Thunderbolt 3 and 4
- Display Port
- 100G Ethernet variants
- High‑speed proprietary SerDes links
Implementation Notes
- Sync header must remain unscrambled
- Scrambler and descrambler must use the same polynomial
- Block alignment relies on detecting the sync header pattern
- Error detection often uses CRC or FEC at higher layers
- Multi‑lane systems require alignment markers
- High‑speed implementations pipeline the scrambler for timing closure
- Parallelization (32/64/128 bits) requires XOR‑matrix expansion
Related Pages
- Line Coding — Overview & Families
- Scrambling — Architecture, Modes & Implementation Notes
- LFSR / PRBS — Overview, Families & Architecture
- 64b/66b Encoding — Architecture & Fundamentals
- PAM4 Signaling — Architecture & Challenges
- Manchester Coding
Summary
- 128b/130b reduces overhead to 1.54%, enabling very high‑speed serial communication.
- Each block contains a 2‑bit sync header and a 128‑bit scrambled payload.
- The sync header identifies data or control blocks and remains unscrambled for alignment.
- The payload is scrambled using a self‑synchronous scrambler based on x^{58}+x^{39}+1.
- The encoder inserts the sync header and scrambles the payload; the decoder detects the header, aligns blocks, and descrambles.
- 128b/130b is used in PCIe, USB4, Thunderbolt, and high‑speed Ethernet.
- It offers excellent spectral properties and efficiency, with the trade‑off of error propagation due to scrambling.
128b/130b is the natural evolution of 64b/66b for multi‑gigabit systems and the foundation of PCIe Gen3+, USB4, and Thunderbolt.
