Physical Layer Interfaces — Overview

Introduction

Physical layer interfaces define the digital connection between the MAC (Media Access Control) and the PHY (Physical Layer). These interfaces specify how data, control information, and management signals are exchanged between the logical protocol engine and the physical transceiver.

They are independent of the electrical signaling used on the physical medium and focus exclusively on the digital protocol boundary between MAC and PHY.

Purpose of MAC‑to‑PHY Interfaces

MAC‑to‑PHY interfaces provide:

• a standardized digital boundary between protocol logic and the physical layer
• interoperability across different PHY implementations
• clear separation between digital and analog domains
• scalability across Ethernet speeds and physical media

They allow system designers to reuse MAC logic with multiple PHY variants and simplify integration across SoCs, FPGAs, and discrete transceivers.

Available MAC‑to‑PHY Interfaces

• MII — Media Independent Interface
  Parallel 4‑bit interface used for 10/100 Mbps Ethernet.
  Provides separate transmit and receive paths, along with control and status signals.
• RMII — Reduced Media Independent Interface
  Reduced‑pin version of MII that uses a shared reference clock and fewer data lines.
  Optimized for low‑pin‑count microcontrollers and compact designs.
• GMII — Gigabit Media Independent Interface
  Parallel 8‑bit interface for 1 Gbps Ethernet.
  Extends the MII concept to support higher throughput while maintaining a similar structure.
• SGMII — Serial Gigabit Media Independent Interface
  Serial version of GMII operating at 1.25 Gbps using 8b/10b encoding.
  Implements a SerDes link between MAC and PHY, replacing the parallel GMII bus.

Digital characteristics

• GMII‑equivalent signaling transported over a serial channel
• embedded auto‑negotiation
• 8b/10b encoded data stream

Electrical characteristics (covered in Electrical Signaling & PHY Interfaces)

• differential CML signaling
• one TX± pair and one RX± pair

T1S 3‑Pin MAC‑to‑PMD Interface

Digital interface specific to 10BASE‑T1S, consisting of three bidirectional signals with dual‑mode behavior (operational mode vs configuration mode).

Operational Mode Signals

• tx — transmit data from MAC to PMD
• rx — receive data from PMD to MAC
• ed — energy detect / error detect from PMD to MAC

Configuration Mode (MDC/MDIO)

During initialization and management, the same pins are repurposed:

• rx → MDC
  Unidirectional clock from MAC to PMD, used to time MDIO transactions.
• ed → MDIO
  Bidirectional open‑drain data line for reading and writing PMD configuration registers.

Key Characteristic

The dual‑mode pin behavior is a defining feature of the 10BASE‑T1S MAC‑to‑PMD interface and distinguishes it from other MAC‑to‑PHY interfaces.

Summary

MAC‑to‑PHY interfaces define the digital boundary between protocol logic and the physical layer.
This page covers the standard interfaces used across Ethernet families, including the specialized 3‑pin interface used by 10BASE‑T1S.
Electrical signaling, analog front‑ends, and PHY‑level characteristics are covered separately in Electrical Signaling & PHY Interfaces — Overview.