SGMII — Serial Gigabit Media Independent

Introduction

The Serial Gigabit Media Independent Interface (SGMII) is a high‑speed serial connection between the MAC and the PHY for 10/100/1000 Mbps Ethernet. It replaces the wide parallel datapaths of MII and GMII with a compact, differential serial link running at 1.25 Gbps. SGMII embeds both data and clock information, reducing pin count and simplifying PCB routing while maintaining compatibility with existing Ethernet speeds.

Interface Signals

SGMII uses a minimal set of differential pairs and management signals:

• TXP / TXN — serial transmit differential pair (MAC to PHY)
• RXP / RXN — serial receive differential pair (PHY to MAC)
• MDC / MDIO — management interface for PHY configuration

The serial link carries:

• 8b/10b encoded data
• embedded clock information
• in‑band signaling for speed and duplex mode

This makes SGMII electrically similar to a low‑speed SerDes link.

Architectural Characteristics

SGMII is built around several architectural principles:

• High‑speed serial signaling — 1.25 Gbps line rate using 8b/10b encoding
• Embedded clock — no separate TX/RX clocks; recovered clock used on the receive side
• Auto‑negotiation in‑band — speed and duplex information transmitted within the serial stream
• Backward compatibility — supports 10/100/1000 Mbps operation
• Reduced pin count — only two differential pairs plus MDIO
• SerDes‑based implementation — typically mapped to FPGA/ASIC transceiver blocks

These characteristics make SGMII ideal for compact, high‑performance designs.

Timing and Clocking Model

SGMII uses a SerDes architecture with:

• 1.25 Gbps serial rate for both TX and RX
• 8b/10b encoding, resulting in 1 Gbps effective data rate
• clock recovery on the receive side
• in‑band signaling to communicate link speed and duplex mode

The MAC typically operates internally at:

• 125 MHz for 1 Gbps
• 25 MHz for 100 Mbps
• 2.5 MHz for 10 Mbps

The PHY communicates the selected speed to the MAC through in‑band control words.

Integration into MAC Architectures

When integrating SGMII into a MAC subsystem:

• TX data must be serialized and 8b/10b encoded
• RX data must be deserialized and decoded
• the recovered clock must be used for RX datapath alignment
• in‑band auto‑negotiation must be interpreted to configure MAC speed
• MDIO must be implemented for PHY configuration and status
• optional elastic buffers may be used to absorb SerDes latency variations

Most FPGA vendors provide dedicated SGMII PHY blocks that handle encoding, decoding, and clock recovery.

RTL Modeling Considerations

An RTL model of SGMII typically includes:

• 8b/10b encoder and decoder
• serializer and deserializer (mapped to SerDes primitives)
• link‑training and synchronization logic
• in‑band auto‑negotiation decoding
• clock‑domain crossing between recovered RX clock and MAC clock
• MDIO controller for PHY register access

These elements allow accurate simulation of SGMII behavior and MAC‑PHY interaction.

Applications

SGMII is used in:

• FPGA‑based Gigabit Ethernet MACs
• network processors and SoCs
• compact embedded systems requiring high throughput
• designs with strict pin‑count or PCB routing constraints
• systems requiring long trace lengths or backplane connectivity

Its combination of high speed and low pin count makes it a popular choice in modern networking architectures.

Standards Reference

SGMII is defined by the Cisco SGMII Specification, complementing IEEE 802.3 by providing a serial MAC‑PHY interface for 10/100/1000 Mbps Ethernet.