MII — Media Independent Interface

Introduction

The Media Independent Interface (MII) defines a parallel digital connection between the MAC and the PHY for 10 Mbps and 100 Mbps Ethernet. It separates data, control, and clock domains in a clean, source‑synchronous architecture that has become the foundation for many later Ethernet interfaces. MII is widely used in embedded systems, FPGAs, and ASICs where deterministic timing and clear signal partitioning are required.

Interface Signals

MII uses a set of transmit, receive, and control signals, each clocked independently:

• TXD[3:0] — transmit data nibble
• TX_EN — transmit enable
• TX_ER — transmit error
• TX_CLK — transmit clock (from PHY to MAC)
• RXD[3:0] — receive data nibble
• RX_DV — receive data valid
• RX_ER — receive error
• RX_CLK — receive clock (from PHY to MAC)
• CRS — carrier sense
• COL — collision detect
• MDC / MDIO — management interface for PHY configuration

The PHY provides both TX_CLK and RX_CLK, ensuring source‑synchronous operation for each direction.

Architectural Characteristics

MII is built around a few key architectural principles:

• Source‑synchronous timing — the PHY provides the clock for both TX and RX paths
• Nibble‑wide datapath — 4‑bit parallel data at 2.5 MHz (10 Mbps) or 25 MHz (100 Mbps)
• Full‑duplex and half‑duplex support — including collision detection and carrier sense
• Clear separation of control and data — simplifying MAC state‑machine design
• Deterministic latency — stable timing relationships across the interface

These characteristics make MII predictable, robust, and easy to integrate into digital systems.

Timing and Clocking Model

MII uses two independent clocks:

• TX_CLK — used by the MAC to launch transmit data
• RX_CLK — used by the MAC to sample receive data

Both clocks are generated by the PHY, ensuring alignment with the physical medium.
In 100 Mbps mode, the clocks run at 25 MHz; in 10 Mbps mode, at 2.5 MHz.

The separation of TX and RX clocks allows the MAC to operate without assumptions about PHY latency or link timing.

Integration into MAC Architectures

When integrating MII into a MAC subsystem:

• TXD and TX_EN must be launched on TX_CLK rising edges
• RXD and RX_DV must be sampled on RX_CLK rising edges
• CRS and COL must be monitored for half‑duplex operation
• TX_ER and RX_ER must be handled for error propagation
• MDC/MDIO must be implemented for PHY configuration and status

The interface maps naturally to synchronous state machines and pipelined datapaths.

RTL Modeling Considerations

An RTL model of MII typically includes:

• TX and RX datapath pipelines
• clock‑domain separation between TX_CLK and RX_CLK
• collision detection logic for half‑duplex
• carrier‑sense handling
• MDIO controller for PHY register access
• optional elastic buffers for timing alignment

These elements allow accurate simulation of MAC‑PHY behavior.

Applications

MII is used in:

• embedded Ethernet controllers
• FPGA‑based MAC implementations
• industrial and automotive Ethernet nodes
• low‑cost networking devices
• systems requiring deterministic 10/100 Mbps connectivity

Its simplicity and clarity make it a common choice in educational and reference designs.

Standards Reference

MII is defined in IEEE 802.3, originally introduced with Fast Ethernet and retained as a baseline interface for many PHYs.