CRC variants differ in polynomial, initialization value, reflection rules, and final XOR settings. This reference page collects the most commonly used CRCs across communication protocols, storage systems, and embedded applications. The list is intentionally focused: many other CRCs exist, but they follow the same general structure and philosophy.
1. CRC‑8 Variants
Name
Polynomial (hex)
Init
XOR Out
RefIn
RefOut
Typical Use
CRC-8 ATM
0x07
0x00
0x00
No
No
ATM, telecom
CRC-8 Maxim
0x31
0x00
0x00
Yes
Yes
1-Wire devices
2. CRC‑16 Variants
Name
Polynomial (hex)
Init
XOR Out
RefIn
RefOut
Typical Use
CRC-16 IBM
0x8005
0x0000
0x0000
Yes
Yes
Legacy protocols
CRC-16 CCITT
0x1021
0xFFFF
0x0000
No
No
Telecom, HDLC
CRC-16 USB
0x8005
0xFFFF
0xFFFF
Yes
Yes
USB packets
3. CRC‑32 Variants
Name
Polynomial (hex)
Init
XOR Out
RefIn
RefOut
Typical Use
CRC-32 Ethernet
0x04C11DB7
0xFFFFFFFF
0xFFFFFFFF
Yes
Yes
Ethernet MAC
CRC-32 Castagnoli
0x1EDC6F41
0xFFFFFFFF
0xFFFFFFFF
Yes
Yes
Storage, iSCSI
CRC-32 MPEG-2
0x04C11DB7
0xFFFFFFFF
0x00000000
No
No
MPEG-2 Transport Stream
4. CRC‑64 Variants
Name
Polynomial (hex)
Init
XOR Out
RefIn
RefOut
Typical Use
CRC-64 ECMA
0x42F0E1EBA9EA3693
0x0000000000000000
0x0000000000000000
No
No
Storage, archives
5. Notes on Variants
CRCs with the same width may behave differently due to reflection, initialization, and final XOR rules.
CRC‑32 Ethernet and CRC‑32 MPEG‑2 share the same polynomial but differ in reflection and final XOR.
CRC‑16 IBM and CRC‑16 USB share the same polynomial but differ in initialization and reflection.
Many additional CRCs exist, but they follow the same structural principles shown here.
CRC – Mathematical Background Algebraic foundations of CRCs, including GF(2) polynomial arithmetic, reflection rules, and serial/parallel formulations.
CRC — Overview, Families & Architecture Architectural principles for CRC computation, including polynomial division, reflection rules, parallel architectures, and integration into streaming datapaths.
CRC – RTL Architecture & Implementation Notes Practical guidelines for implementing CRC generators and checkers in hardware, derived from the underlying algebraic and parallelization rules.
LFSR & PRBS — Overview, Families & Architecture Provides a unified view of Linear Feedback Shift Registers and Pseudo‑Random Binary Sequences, covering architectural principles, polynomial families, implementation trade‑offs, and their role in line coding, scrambling, and verification flows.
Data Path – Architecture & Fundamentals Integration of CRC computation into streaming datapaths, including placement, pipelining, and flow‑control considerations.
Pipelining – Architecture & Fundamentals Architectural techniques used to balance CRC computation latency, improve timing closure, and maintain full‑rate throughput.
