CRC – RTL Architecture & Implementation Notes

CRC blocks are typically implemented as Linear Feedback Shift Registers (LFSRs) that realize the modulo‑2 division defined by the generator polynomial. Depending on throughput requirements, the architecture may be serial, parallel, or fully pipelined. This page describes the most common RTL structures, interface conventions, and practical considerations for integrating CRC logic into MACs, PHYs, and protocol engines.

1. Serial CRC Architecture

The serial CRC is the closest representation of the mathematical definition. It processes one bit per cycle and is often used as a reference model or as the basis for generating parallel equations.

• One input bit per clock cycle.
• LFSR feedback defined by the generator polynomial.
• Minimal area, higher latency.
• Useful for low‑speed systems or verification.

Key characteristics:

• crc_reg updated every cycle.
• Conditional XOR based on the input bit.
• Reset to the initial value (Init).
• Final XOR applied at the end of the frame.

2. Parallel CRC Architecture

Parallel CRCs update the CRC state using N input bits per cycle. This is the architecture used in Ethernet MACs and other high‑throughput systems.

• Typical widths: 4, 8, 16, or 32 bits.
• XOR equations derived by unrolling the serial LFSR.
• XOR depth increases with input width.
• May require pipelining for high‑frequency operation.

General structure:

• CRC register (16, 32, or 64 bits).
• Combinational XOR matrix combining:
  • selected bits of the current CRC
  • selected bits of the input word
• Optional pipeline stages.

3. Pipelined CRC

High‑speed systems (10G, 25G, 40G, 100G) often require pipelined CRC logic.

• Parallel equations split across multiple stages.
• Increased latency, higher maximum clock frequency.
• Suitable for deep datapaths and multi‑stage MAC pipelines.

Typical use cases:

• 10G/25G/40G Ethernet MACs.
• High‑speed DSP pipelines.
• Storage controllers.

4. Reflection, Bit Ordering, and Endianness

CRC implementations differ based on:

• input reflection (RefIn)
• output reflection (RefOut)
• bit ordering (LSB‑first vs MSB‑first)
• bus endianness

These parameters affect:

• the LFSR structure
• the parallel XOR equations
• verification against standard test vectors

Example:

• CRC‑32 Ethernet uses LSB‑first and reflection.
• CRC‑32 MPEG‑2 uses MSB‑first and no reflection.

5. Typical RTL Interface

A CRC block usually exposes the following signals:

• data_in[N-1:0] — parallel input word
• data_valid — input word is valid
• data_last — last word of the frame
• crc_out[M-1:0] — current CRC value
• crc_valid — final CRC is ready
• init — load initial CRC value
• enable — update enable

Integration notes:

• Update CRC only when data_valid = 1.
• Apply final XOR before output.
• In RX paths, compare computed CRC with received FCS.

6. Integration in a MAC

For Ethernet:

• CRC is computed over the entire frame except the FCS.
• Final CRC must be inverted (XOR with 0xFFFFFFFF).
• In RX, the computed CRC must match the received FCS.
• CRC must not update during idle or gap cycles.

Typical pipeline:

1. Ingress FIFO
2. CRC update
3. Optional pipeline
4. Output stage
5. FCS append (TX) or FCS check (RX)

7. RTL Implementation Notes

• Use registers to reduce XOR depth.
• For wide inputs (32 bits), consider 2–3 pipeline stages.
• Always verify with standard test vectors (“123456789”).
• Use scripts to generate parallel equations (Python recommended).
• Reflection errors are the most common source of mismatches.

8. GitHub Repository Structure

The CRC directory in the repository includes:

• crc32_eth_serial.vhd
• crc32_eth_4bit.vhd
• crc32_eth_8bit.vhd
• crc32_eth_32bit.vhd
• crc16_ccitt_8bit.vhd
• tb_crc32_eth.vhd
• README.md with:

• polynomial definitions
• configuration parameters
• test vectors
• usage examples

A direct link to the GitHub folder can be added here.

9. Related Pages

• CRC – Mathematical Background
  Algebraic foundations of CRCs, including GF(2) polynomial arithmetic, reflection rules, and serial/parallel formulations.
• CRC — Overview, Families & Architecture
  Architectural principles for CRC computation, including polynomial division, reflection rules, parallel architectures, and integration into streaming datapaths.
• CRC – Verification & Test Vectors
  Practical test vectors and verification guidelines for validating CRC implementations.
• LFSR / PRBS — Overview, Families & Architecture
  Shared mathematical foundations with CRC architectures, including polynomial arithmetic and feedback structures.
• Data Path – Architecture & Fundamentals
  Integration of CRC computation into streaming datapaths, including placement, pipelining, and flow‑control considerations.
• Flow Control – Architecture & Fundamentals
  Mechanisms that regulate data movement and ensure correct CRC alignment, insertion, and checking within streaming pipelines.
• Pipelining – Architecture & Fundamentals
  Architectural techniques used to balance CRC computation latency, improve timing closure, and maintain full‑rate throughput.