CDC — Asynchronous FIFO Architecture
Introduction
Asynchronous FIFOs are the most robust and widely used structures for transferring multi‑bit data between unrelated clock domains. Unlike single‑bit synchronizers or handshake‑based schemes, asynchronous FIFOs decouple write and read timing entirely, allowing each domain to operate independently while maintaining data integrity, ordering, and flow control.
This page presents the architectural principles, pointer structures, and design considerations that make asynchronous FIFOs reliable across a wide range of applications.
Scope
This page focuses on the architecture and operation of asynchronous FIFOs, including pointer encoding, synchronization strategy, and full/empty detection. Safety‑related considerations and metastability analysis are covered in the related CDC pages.
Architectural Overview
An asynchronous FIFO consists of two independent clock domains:
- Write domain (clk_w) — produces data
- Read domain (clk_r) — consumes data
The two domains interact only through:
- a shared memory array
- Gray‑coded write and read pointers
- synchronized pointer values used for full/empty detection
No multi‑bit data crosses the domain boundary directly; only encoded pointers do.
Figure 1 — Asynchronous FIFO Architecture
Conceptual architecture of an asynchronous FIFO, showing Gray‑coded pointers, pointer synchronization, dual‑port memory, and full/empty detection across independent clock domains.
Key Structures
FIFO Memory Array
A dual‑port RAM or register array accessible from both clock domains.
- Write operations occur under
clk_w - Read operations occur under
clk_r
Write Pointer (Gray‑coded)
- Incremented in the write domain
- Converted to Gray code
- Synchronized into the read domain
Read Pointer (Gray‑coded)
- Incremented in the read domain
- Converted to Gray code
- Synchronized into the write domain
Pointer Synchronization
Gray‑coded pointers are passed through multi‑stage synchronizers to avoid metastability propagation.
Full/Empty Logic
- Empty when synchronized write pointer equals read pointer
- Full when write pointer is one cycle behind read pointer in Gray space
These comparisons are performed entirely within each domain using synchronized pointers.
Why Gray Code?
Gray code ensures that only one bit changes at a time when a pointer increments. This prevents incoherent sampling of multi‑bit binary counters, which could otherwise produce incorrect full/empty decisions.
Design Considerations
FIFO Depth
Must accommodate burstiness and clock‑frequency differences.
Pointer Width
Determines FIFO depth and affects synchronization latency.
Latency
Includes:
- write latency
- read latency
- pointer synchronization latency
Metastability Containment
Only pointer bits may become metastable; data never crosses domains directly.
Full/Empty Robustness
Incorrect pointer synchronization can cause:
- false full
- false empty
- data overwrite or underflow
Safety Extensions
High‑integrity systems may include:
- redundant pointer synchronizers
- parity‑protected pointers
- plausibility checks on pointer progression
- diagnostic counters for overflow/underflow events
Related Technical Pages
- Clock Domain Crossing — Architecture & Fundamentals
- Clock Domain Crossing — Practical Guidelines
- CDC — Synchronization Techniques
- CDC — Metastability and Timing
