CDC — Synchronization Techniques
Introduction
Synchronization techniques are the foundation of safe and deterministic communication between asynchronous or mesochronous clock domains. This page presents the architectural patterns used to transfer single‑bit events, multi‑bit values, and control signals across unrelated clocks, focusing on universally applicable structures rather than implementation‑specific details.
Scope
This page covers the main synchronization schemes used in digital systems, including their operating principles, assumptions, and typical use cases. Metastability theory, MTBF analysis, and FIFO‑based data transfer are covered in the dedicated pages CDC — Metastability and Timing and CDC — Asynchronous FIFO Architecture.
Architectural Overview
Synchronization techniques fall into three broad categories:
Single‑Bit Synchronization
Used for level or pulse signals that represent events or control conditions.
Multi‑Bit Synchronization
Used when multiple bits must cross a domain boundary coherently.
Protocol‑Based Synchronization
Used when data transfer requires acknowledgment, ordering, or flow control.
Each category has strengths, limitations, and assumptions about timing, latency, and signal behavior.
Key Techniques
Single‑Bit Synchronization
Multi‑Stage Synchronizer (FF1 → FF2)
- Most common structure for single‑bit CDC
- Reduces metastability probability
- Assumes the signal is stable long enough to be sampled
Pulse Stretching / Pulse Synchronization
- Ensures short pulses are visible in the destination domain
- Often implemented with toggle or handshake schemes
Toggle Synchronizer
- Encodes events as transitions rather than levels
- Robust for sporadic or narrow pulses
Multi‑Bit Synchronization
Gray‑Coded Values
- Only one bit changes at a time
- Used for pointers, counters, and state indicators
One‑Hot or One‑Cold Encodings
- Ensures only one active bit
- Useful for state machines crossing domains
Parity‑Protected Transfers
- Detects incoherent multi‑bit sampling
- Often combined with retry or handshake
Protocol‑Based Synchronization
Request/Acknowledge Handshake
- Deterministic transfer with explicit confirmation
- Works for single‑bit or multi‑bit data
- Can be hardened with timeout or redundancy
Ready/Valid Schemes (with CDC wrappers)
- Used in streaming architectures
- Requires careful adaptation to asynchronous domains
Token‑Based or Credit‑Based Schemes
- Used in high‑throughput or pipelined systems
- Ensures ordering and flow control
Design Considerations
Latency
Each technique introduces different latency characteristics (e.g., 2–3 cycles for synchronizers, variable for handshake).
Throughput
Some schemes support only sporadic events; others support continuous data flow.
Glitch Sensitivity
Asynchronous transitions may create spurious pulses unless properly filtered.
Assumptions About Signal Behavior
- Stability window
- Maximum toggle rate
- Monotonicity (for counters)
Safety and Diagnostic Extensions
- Redundant synchronizers
- Plausibility checks
- Timeout detection
- Error counters
Related Technical Pages
- Clock Domain Crossing — Architecture & Fundamentals
- Clock Domain Crossing — Practical Guidelines
- CDC — Metastability and Timing
- CDC — Asynchronous FIFO Architecture
