CDC — Metastability and Timing
Introduction
Metastability is an inherent phenomenon in digital systems whenever a signal is sampled without meeting setup and hold requirements. In clock‑domain crossing (CDC) structures, metastability cannot be eliminated, but its effects can be controlled through architectural techniques, timing assumptions, and synchronizer design. This page provides the conceptual and mathematical foundations needed to reason about metastability, timing uncertainty, and the reliability of CDC structures.
Scope
This page covers the principles of metastability, the factors that influence its duration, and the timing considerations that determine the reliability of synchronizers. It focuses on universally applicable concepts rather than device‑specific parameters. FIFO‑based data transfer and synchronization schemes are covered in the related CDC pages.
Metastability Fundamentals
What Is Metastability?
A flip‑flop enters a metastable state when its input changes too close to the sampling edge, violating setup or hold time. In this state:
- the output is neither a valid ‘0’ nor ‘1’
- the resolution time is unpredictable
- the output may oscillate or settle slowly
Resolution Behavior
Metastability resolves exponentially over time. The probability that a flip‑flop remains metastable after time ( t ) is approximately:
where:
- ( \tau ) is the device‑specific time constant
- larger ( t ) reduces the probability of metastability propagation
MTBF (Mean Time Between Failures)
The reliability of a synchronizer is often expressed as: where:
- ( T_r ) is the available resolution time
- ( f_{clk} ) is the destination clock frequency
- ( f_{data} ) is the toggle rate of the asynchronous signal
Increasing resolution time or reducing toggle rate improves MTBF.
Timing Considerations in CDC
Resolution Time in Multi‑Stage Synchronizers
A two‑stage synchronizer provides one full clock period for metastability resolution. Additional stages increase resolution time but add latency.
Setup/Hold Margins
Even though CDC signals are asynchronous, synchronizer flip‑flops must still meet internal timing requirements to avoid excessive metastability.
Clock Frequency Effects
Higher destination clock frequencies reduce resolution time and therefore reduce MTBF.
Data Toggle Rate
Signals that toggle frequently increase the probability of sampling during a vulnerable window.
Glitch Sensitivity
Asynchronous glitches effectively increase the toggle rate and reduce MTBF.
Architectural Techniques for Managing Metastability
Multi‑Stage Synchronizers
- Increase resolution time
- Reduce metastability propagation probability
- Common for single‑bit CDC
Hardened Flip‑Flops
- Lower ( \tau )
- Improve MTBF without adding latency
Pulse‑Stretching and Toggle Schemes
- Reduce effective toggle rate
- Improve sampling reliability
Encoded Multi‑Bit Transfers
- Gray code ensures only one bit changes at a time
- Reduces incoherent sampling risk
FIFO‑Based Transfers
- Avoid multi‑bit sampling entirely
- Use pointer synchronization instead of data synchronization
Design Considerations
Latency vs. Reliability
More synchronizer stages increase MTBF but add latency.
Technology and PVT Variations
Metastability parameters vary with:
- process corner
- voltage
- temperature
Safety‑Critical Systems
High‑integrity designs may require:
- redundant synchronizers
- metastability event counters
- plausibility checks
Related Technical Pages
- Clock Domain Crossing — Architecture & Fundamentals
- Clock Domain Crossing — Practical Guidelines
- CDC — Synchronization Techniques
- CDC — Asynchronous FIFO Architecture
