PMD — 10BASE‑T1S 3‑Pin Interface

Introduction

The 10BASE‑T1S Physical Medium Dependent (PMD) interface defines a compact, three‑wire digital connection between the MAC and the PMD sublayer of a 10BASE‑T1S PHY. Unlike traditional Ethernet interfaces, the PMD for 10BASE‑T1S reuses the same pins for both configuration and operational modes, enabling extremely low pin count and simplified integration.
The interface is designed for single‑pair Ethernet in multidrop topologies and relies on PLCA (Physical Layer Collision Avoidance) to provide deterministic, collision‑free operation after initial slot acquisition.

Interface Signals

The PMD interface exposes three bidirectional digital signals toward the MAC:

• tx — transmit data toward the PMD
• rx — receive data from the PMD, or MDC during configuration
• ed — energy/error detect during operation, or MDIO during configuration

This dual‑mode behavior is a defining characteristic of the 10BASE‑T1S PMD interface.

Configuration Mode (MDC/MDIO)

Before entering normal operation, the PMD uses a standard management interface:

• rx → MDC
  • unidirectional clock from MAC to PMD
  • used to time MDIO transactions
• ed → MDIO

• bidirectional open‑drain data line
• used for reading and writing PMD configuration registers

This mode is active during initialization and link setup.

Operation Mode (RX/ED)

After configuration, the interface transitions to operational mode:

• rx becomes the receive data signal from the PMD
• ed becomes Energy Detect / Error Detect

Energy Detect

ED indicates medium activity:

• another node is transmitting
• the medium is idle between transmissions

Error Detect

ED asserts error conditions when:

• physical signal edges violate timing or amplitude specifications
• invalid symbols or disturbances are detected
• two nodes transmit simultaneously during slot acquisition (the only moment where collisions may occur)

Once PLCA synchronization is complete, collisions do not occur during normal operation.

Architectural Characteristics

The PMD interface is designed around several principles:

• Minimal pin count — only three digital signals toward the MAC
• Dual‑mode signaling — RX/ED reused as MDC/MDIO during configuration
• PLCA‑based access control — deterministic, collision‑free operation after slot assignment
• Error detection — ED reports physical‑layer violations and slot‑acquisition conflicts
• Synchronous operation — TX, RX, and ED are aligned to the MAC/PMD clock domain

This architecture is ideal for embedded, automotive, and industrial systems requiring low cost and high robustness.

Timing and Clocking Model

The PMD uses a simple synchronous timing model:

• TX and RX transitions are aligned to the system clock shared by MAC and PMD logic
• ED is sampled synchronously to detect:

• medium activity
• physical‑layer violations
• slot‑acquisition collisions

PLCA ensures that, once the network is synchronized, only one node transmits in each slot, eliminating collisions during normal operation.

Integration into MAC Architectures

When integrating the PMD interface:

• TX is driven only during the node’s assigned PLCA slot
• RX is sampled continuously to receive frames and PLCA beacons
• ED is monitored to detect medium activity and physical errors
• slot index, beacon timing, and deferral logic may be implemented in:

• the MAC
• a dedicated PLCA block
• a MAC‑PMD wrapper

The PMD handles physical encoding and decoding, while PLCA ensures deterministic access to the shared medium.

RTL Modeling Considerations

An RTL model of the PMD typically includes:

• bidirectional handling of RX/MDC and ED/MDIO
• TX serialization and shaping
• RX sampling and symbol decoding
• ED generation for energy and error conditions
• PLCA‑aware slot‑acquisition collision detection
• timing alignment with the MAC clock domain
• optional test hooks for multidrop arbitration scenarios

This structure matches the behavior of your existing RTL entity.

Applications

The PMD interface is used in:

• automotive zonal architectures
• industrial multidrop networks
• low‑cost embedded Ethernet nodes
• sensor/actuator clusters
• deterministic real‑time communication systems

Its simplicity and dual‑mode signaling make it ideal for compact, cost‑sensitive designs.

Standards Reference

The 3‑pin PMD interface is defined by the Open Alliance 10BASE‑T1S specification, complementing IEEE 802.3cg by providing a practical MAC‑to‑PMD interconnect for multidrop single‑pair Ethernet.