MAC / PCS / PHY — Roles & Interactions

Introduction

Modern digital communication systems rely on a layered architecture where the Physical Layer (PHY), Physical Coding Sublayer (PCS), and Media Access Control (MAC) each play a distinct and well‑defined role.
Together, these layers transform raw bits into structured frames, manage access to the communication medium, and ensure reliable transmission across a wide range of channels and technologies.

This page describes the responsibilities of each layer, how they interact, and how data flows from the logical packet domain down to the physical signaling domain.

Layer Responsibilities

PHY — Physical Layer

The PHY is responsible for the electrical or optical transmission of bits.
Its functions include:

serialization and deserialization
equalization (TX FFE, RX CTLE/DFE)
clock recovery and phase alignment
symbol mapping and line coding
lane bonding and alignment markers (multi‑lane PHYs)

The PHY operates entirely in the analog and symbol domain. It does not understand packets, headers, or addresses.

PCS — Physical Coding Sublayer

The PCS acts as a bridge between the MAC and the PHY.
Its responsibilities include:

symbol encoding and decoding
scrambling and descrambling
block framing (e.g., 64b/66b, 128b/130b)
alignment markers and lane deskew
control code insertion (e.g., ordered sets, idle symbols)
error detection at the block level

The PCS introduces structure into the bitstream, enabling synchronization, alignment, and error detection before the data reaches the MAC.

MAC — Media Access Control

The MAC is the first layer that operates on packets rather than symbols or blocks.
Its responsibilities include:

frame construction and parsing
addressing and protocol fields
metadata handling
medium access control (for shared media)
protocol‑level flow control (credits, pause frames, etc.)
error detection using CRC

The MAC defines the logical format of packets and manages how they are transmitted and received.

Data Flow Across Layers

From MAC to PHY (Transmit Path)

MAC constructs a frame with headers, payload, and CRC.
PCS encodes the frame into blocks, scrambles it, inserts alignment markers, and generates control symbols.
PHY converts the blocks into symbols, applies equalization, serializes the data, and transmits it over the physical channel.

From PHY to MAC (Receive Path)

PHY receives the analog signal, recovers the clock, equalizes the waveform, and deserializes the bitstream.
PCS descrambles the data, decodes blocks, aligns lanes, and identifies control symbols.
MAC parses the frame, validates the CRC, extracts metadata, and forwards the packet to upper layers.

This pipeline ensures a clean separation between physical signaling, symbol/block processing, and packet‑level logic.

Interactions Between Layers

MAC ↔ PCS Interface

The MAC provides:

frames
metadata (length, type, priority)
control information (start/end of frame)

The PCS provides:

block‑level status
error indications
flow control signals (depending on protocol)

This interface is typically parallel and synchronous, optimized for packet throughput.

PCS ↔ PHY Interface

The PCS provides:

encoded blocks
control symbols
alignment markers
lane mapping information

The PHY provides:

symbol lock and block lock status
error counters
lane alignment status
link training feedback (for adaptive PHYs)

This interface is often symbol‑based and may span multiple lanes.

Multi‑Lane Architectures

Modern high‑speed protocols often use multiple lanes to achieve higher throughput.
In these systems:

The MAC sees a single logical data stream.
The PCS distributes blocks across lanes and inserts alignment markers.
The PHY transmits each lane independently with its own CDR and equalization.

The PCS is responsible for:

lane bonding
deskew
alignment marker detection
reassembly of the original data stream

This allows the MAC to remain completely unaware of the physical lane structure.

Error Handling Across Layers

PHY-Level Errors

symbol errors
loss of lock
equalization failures
lane deskew errors

PCS-Level Errors

block decode errors
invalid control symbols
alignment marker mismatches
descrambler lock loss

MAC-Level Errors

CRC failures
frame length violations
malformed headers

Each layer handles errors appropriate to its domain, ensuring robustness and isolation.

Real‑World Examples

Ethernet

PHY: electrical/optical signaling (10BASE‑T → 800G)
PCS: 64b/66b, 256b/257b, RS‑FEC
MAC: frame format, addressing, pause frames

PCIe

PHY: PAM4/NRZ SERDES
PCS: 128b/130b encoding, scrambling, ordered sets
MAC: TLP construction, flow control, CRC

USB4

PHY: high‑speed differential signaling
PCS: framing, scrambling, lane bonding
MAC: packet routing, flow control, protocol management

These examples show how the same layering principles apply across very different technologies.

Summary

The MAC, PCS, and PHY layers form the backbone of modern digital communication.
Each layer has a distinct role:

the PHY transmits bits,
the PCS structures and aligns data,
the MAC constructs and interprets packets.

Understanding how these layers interact is essential for designing reliable, scalable, and interoperable communication systems.

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