Ethernet — MAC / PCS / PMA Architecture

Introduction

Ethernet is one of the most widely adopted communication standards in networking, data centers, and high‑speed interconnects.
Its architecture is built around a clean separation of responsibilities across the MAC, PCS, and PMA/PHY layers, enabling scalability from 10 Mbps to 800 Gbps while preserving interoperability and backward compatibility.

This page describes the architecture of Ethernet’s MAC, PCS, and PMA layers, their responsibilities, how they interact, and how data flows across the link.

Layering Overview

Ethernet is structured into three major sublayers:

• MAC (Media Access Control)
  • frame construction and parsing
  • addressing and protocol identification
  • CRC generation and validation
  • flow control (pause, PFC)
• PCS (Physical Coding Sublayer)
  • block encoding (64b/66b, 256b/257b)
  • scrambling and descrambling
  • alignment markers
  • lane distribution and deskew
  • error detection at block level
• PMA / PHY (Physical Medium Attachment / Physical Layer)

• SERDES
• equalization and CDR
• lane bonding
• electrical/optical signaling

This architecture allows Ethernet to evolve its physical layer without changing the MAC.

MAC Layer

Responsibilities

The MAC layer operates entirely in the packet domain and is responsible for:

• constructing Ethernet frames
• adding source/destination MAC addresses
• inserting EtherType or length fields
• generating and checking CRC‑32
• handling VLAN tags (if present)
• enforcing minimum inter‑packet gap
• implementing flow control (pause frames, PFC)

Frame Structure

A typical Ethernet frame includes:

• Destination MAC
• Source MAC
• VLAN tags (optional)
• EtherType / Length
• Payload
• CRC‑32

The MAC defines the logical packet format used across all Ethernet speeds.

PCS Layer

Responsibilities

The PCS introduces structure into the bitstream and prepares data for physical transmission:

• block encoding (64b/66b for 10G/25G/40G/100G, 256b/257b for 400G/800G)
• scrambling to improve spectral properties
• insertion of control blocks and ordered sets
• alignment marker insertion for multi‑lane links
• block lock and error detection
• lane distribution and deskew

Encoding Evolution

Ethernet PCS encoding evolved as speeds increased:

• 8b/10b for 1G/2.5G/5G
• 64b/66b for 10G/25G/40G/100G
• 256b/257b for 400G/800G

Higher‑order encodings reduce overhead and improve efficiency.

PMA / PHY Layer

Responsibilities

The PMA/PHY layer handles the physical transmission of bits:

• SERDES serialization/deserialization
• TX equalization (FFE)
• RX equalization (CTLE, DFE)
• clock recovery and phase alignment
• lane bonding and alignment
• electrical or optical signaling

The PHY is unaware of frames or blocks; it operates on symbols and analog waveforms.

Data Flow Across Layers

Transmit Path

1. MAC constructs the Ethernet frame and appends CRC‑32.
2. PCS encodes the frame into blocks, scrambles data, inserts alignment markers, and distributes blocks across lanes.
3. PMA/PHY serializes the blocks, applies equalization, and transmits them over copper or fiber.

Receive Path

1. PMA/PHY receives the signal, equalizes, recovers the clock, and deserializes the bitstream.
2. PCS descrambles, decodes blocks, aligns lanes, and detects control blocks.
3. MAC extracts the frame, validates CRC‑32, and forwards the packet to upper layers.

Multi‑Lane Operation

Modern Ethernet speeds (40G, 100G, 200G, 400G, 800G) use multiple lanes:

• PCS distributes blocks across lanes
• alignment markers allow deskew
• PMA handles independent CDR per lane
• MAC remains unaware of lane structure

This enables scaling bandwidth without redesigning the MAC.

Flow Control

Ethernet supports two flow control mechanisms:

• Pause frames (802.3x) — stop all traffic temporarily
• Priority‑based Flow Control (PFC) — pause specific priorities

Flow control is implemented at the MAC layer and influences scheduling and buffer management.

Error Handling

PCS-Level Errors

• block decode errors
• invalid control blocks
• alignment marker mismatches
• descrambler lock loss

MAC-Level Errors

• CRC‑32 failures
• frame length violations
• malformed headers

Each layer handles errors appropriate to its domain.

Real‑World Examples

10GBASE‑R

• 64b/66b encoding
• single lane
• PCS scrambling
• standard MAC frame format

100GBASE‑KR4

• 4 lanes
• alignment markers
• lane deskew
• FEC at PCS

400GBASE‑FR4

• PAM4 signaling
• 256b/257b encoding
• advanced equalization
• multi‑lane PCS

Ethernet’s architecture allows dramatic PHY evolution while keeping MAC unchanged.

Related Pages

• MAC / PCS / PHY — Roles & Interactions
• Scrambling & Descrambling — Architecture & Use Cases
• Packetization — Architecture & Data Flow
• Protocol Flow Control — Architecture & Mechanisms
• CRC — Overview, Families & Architecture
• PCIe — Transaction Layer & Data Flow
• USB / USB4 — Packet Architecture & Flow Control

Summary

Ethernet’s MAC/PCS/PMA architecture provides a clean separation between packet processing, block encoding, and physical signaling.
This modularity enables Ethernet to scale from Mbps to hundreds of Gbps while preserving interoperability and backward compatibility.
Understanding these layers is essential for designing high‑performance Ethernet endpoints, switches, and PHYs.