FIFO — Architecture Basics

Introduction

This Design Note provides a concise overview of FIFO (First‑In, First‑Out) architectures commonly used in digital systems. Although FIFO implementations vary depending on throughput, latency, and protocol requirements, the fundamental concepts remain consistent across most designs. This note serves as a conceptual foundation for understanding the AXI4‑Stream FIFO published in the RTL Library.

FIFO Fundamentals

A FIFO is a queue‑based storage element where data is read in the same order it was written.

It is typically used for:

buffering between asynchronous or decoupled domains
absorbing bursty traffic
handling backpressure
aligning timing between producer and consumer
protocol adaptation

A FIFO must guarantee:

ordering (no reordering of entries)
integrity (no data loss or duplication)
flow control (full/empty detection)

Core Components

Memory Array

A circular buffer implemented using:

registers (small FIFOs)
block RAM (large FIFOs)
distributed RAM (medium size, FPGA‑dependent)

Write Pointer

Tracks the next location to store incoming data.

Read Pointer

Tracks the next location to output data.

Occupancy Counter

Tracks the number of stored elements. Used for:

full detection
empty detection
almost‑full / almost‑empty thresholds

Control Logic

Implements:

pointer increment
wrap‑around
simultaneous read/write handling
flow control signals

Pointer and Counter Behavior

A FIFO uses modular arithmetic to wrap pointers:

wr_ptr_next = (wr_ptr + 1) mod DEPTH
rd_ptr_next = (rd_ptr + 1) mod DEPTH

The occupancy counter updates as:

if write and not read: count = count + 1
if read and not write: count = count - 1
if read and write:     count unchanged

This ensures stable behavior even when reads and writes occur in the same cycle.

Full and Empty Conditions

Empty

count = 0

No valid data is available for reading.

Full

count = DEPTH

No additional data can be written.

Simultaneous Read/Write

If both operations occur in the same cycle:

pointers advance independently
count remains unchanged
no overflow or underflow occurs

This is a key property of well‑designed FIFOs.

Handling Sideband Signals

Many protocols require additional metadata to travel with the data:

TLAST (AXI4‑Stream)
TKEEP
parity bits
error flags
packet boundaries

A FIFO must store these sideband signals in parallel with the data word.

Example (conceptual):

fifo_entry = { data, last, keep, error }

This ensures protocol‑level correctness.

Backpressure and Flow Control

A FIFO must correctly handle situations where:

the producer is faster than the consumer
the consumer temporarily stops accepting data

Write Side

The FIFO asserts ready = 0 when full.

Read Side

The FIFO asserts valid = 0 when empty.

This mechanism prevents:

overflow
underflow
data corruption

Timing Considerations

FIFO timing depends on:

memory type (registers vs BRAM)
synchronous vs asynchronous design
registered outputs
pipeline stages

Typical trade‑offs:

Feature	Benefit	Cost
Registered output	Higher Fmax	+1 cycle latency
BRAM‑based FIFO	Large depth	Higher access latency
Distributed RAM	Good density	Lower Fmax on large widths

Common Corner Cases

A robust FIFO must handle:

pointer wrap‑around
simultaneous read/write
reset during active traffic
TLAST alignment
empty‑to‑non‑empty transitions
full‑to‑non‑full transitions

These cases are often validated through simulation waveforms.

Minimal Conceptual Diagram (ASCII)

                +---------------------------+
Write Interface |  wr_en   wr_data  wr_last |
                +---------------------------+
                           |
                           v
                +---------------------------+
                |       FIFO Memory         |
                |  circular buffer (DEPTH)  |
                +---------------------------+
                           ^
                           |
Read Interface  +---------------------------+
                |  rd_en   rd_data  rd_last |
                +---------------------------+

Relation to AXI4‑Stream FIFO

The AXI4‑Stream FIFO published in the RTL Library is a direct application of these principles:

circular buffer
pointer‑based addressing
count‑based full/empty detection
TLAST propagation
stable behavior under backpressure

This Design Note provides the conceptual foundation for understanding that implementation.

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