Arbiter — Architecture & Fundamentals

A core decision‑making block for resource sharing and flow control.

1. Introduction

An arbiter is a fundamental building block used whenever multiple requesters need controlled access to a shared resource:

• a bus
• a memory port
• a communication channel
• a functional unit
• a shared buffer

Its job is simple in concept:
decide who gets access next.

But behind this simplicity lies a rich set of architectural and implementation choices that deeply influence system performance, fairness, latency, and predictability.

This page introduces the architecture, behavior, and design considerations of arbiters, and explains how they fit into both system‑level and block‑level design.

2. What an Arbiter Does

An arbiter receives multiple request signals and produces one grant signal at a time.

Typical use cases:

• bus arbitration
• DMA channel selection
• router port selection
• shared memory access
• multi‑master interfaces
• packet scheduling

Arbiters are everywhere — from simple microcontrollers to complex SoCs and network fabrics.

3. Arbiter Architecture Overview

A generic arbiter consists of:

• Request inputs
• Grant outputs
• Priority logic
• State machine (for fairness or round‑robin)
• Optional masking logic
• Optional lock/hold mechanism

Block Diagram (concept)

   Req[0] ──┐
   Req[1] ──┼──►  Arbiter Core  ───► Grant[N]
   Req[2] ──┤
   ...      │
   Req[N] ──┘

Types of Arbiters

A) Fixed‑Priority Arbiter

• Each requester has a static priority
• Simple, fast, deterministic
• Risk of starvation for low‑priority requesters

B) Round‑Robin Arbiter

• Priority rotates after each grant
• Guarantees fairness
• Slightly more complex

C) Masked Round‑Robin

• Round‑robin with dynamic masking
• Useful when some requesters must be temporarily excluded

D) Weighted Arbiter

• Each requester has a weight
• Used in QoS systems
• More complex state machine

E) Time‑Division Arbiter

• Grants follow a fixed schedule
• Used in deterministic real‑time systems

5. Key Concepts

A) Fairness

Ensures that all requesters eventually receive service.

B) Starvation

Occurs when a requester is perpetually ignored.

C) Latency

Time between request and grant.

D) Throughput

How efficiently the arbiter keeps the shared resource busy.

E) Determinism

Critical in real‑time and safety‑critical systems.

6. System‑Level Perspective

From a system‑level viewpoint, an arbiter is a policy enforcement mechanism.

It determines:

• fairness
• latency distribution
• bandwidth allocation
• contention behavior
• quality of service

A system architect chooses the arbiter type based on:

• real‑time constraints
• throughput requirements
• fairness guarantees
• starvation tolerance
• power and area budgets

Examples:

• A DMA engine may use round‑robin for fairness
• A safety‑critical bus may use fixed priority
• A network router may use weighted arbitration

7. Block‑Level Perspective

At block level, an arbiter is an RTL module with:

• combinational priority logic
• optional state machine
• optional masking
• optional lock/hold logic

Key implementation topics:

• one‑hot vs binary grant encoding
• priority encoder design
• fairness state machine
• timing closure
• glitch‑free grant signals
• reset behavior

Common pitfalls:

• combinational loops
• starvation in fixed‑priority designs
• incorrect rotation in round‑robin
• metastability if requests come from different domains

8. Related Content

Design Notes

(Quando vorrai, potremo creare una Design Note dedicata agli arbitri.)

Learning Paths

• Block‑Level Design Path
  Arbiter as a core RTL decision‑making block
• System‑Level Design Path
  Arbiter as a policy mechanism for resource sharing

9. Summary

Arbiters are simple in concept but deeply influential in system behavior.
They define how resources are shared, how fairness is enforced, and how contention is resolved.

Understanding arbiters is essential for:

• system architects
• RTL designers
• protocol designers
• network‑on‑chip engineers
• real‑time system developers

This page serves as the foundation for more advanced topics such as:

• QoS scheduling
• bus architectures
• NoC routers
• DMA engines
• multi‑master systems

10. Related Pages

• Data Path — Architecture & Fundamentals
  The structural backbone that defines how data moves through a system, how throughput and latency are balanced, and how arbitration interacts with flow‑control and pipeline stages.
• FIFO — Architecture & Fundamentals
  Elastic buffering structures that often sit downstream of arbiters to absorb burstiness, decouple timing, and manage multi‑source traffic.
• FSM — Architecture & Fundamentals
  Deterministic control logic frequently used to implement arbitration policies, manage grant sequencing, and coordinate multi‑client protocols.
• Flow Control — Architecture & Fundamentals
  Mechanisms that regulate data movement, backpressure propagation, and fairness, directly influencing arbiter behavior and request/grant timing.
• CRC — Overview, Families & Architecture
  Error‑detection blocks commonly placed after arbitration points in packet‑based or multi‑stream datapaths.