Block-Level Design

The Digital Design path focuses on the principles and methods used to build digital hardware. It covers logic, combinational and sequential structures, timing, state machines, and the design flow that connects specifications to real implementations.

The goal is to understand how digital systems behave, how they are described, and how they are verified. The path does not depend on a specific language or tool: the concepts apply to any HDL and to any design environment.

This section prepares you for more advanced topics such as system architecture, FPGA prototyping, and hardware–software interaction.

Core Building Blocks

FIFO — Architecture & Fundamentals
A foundational RTL building block used for buffering, CDC, and flow control.

Arbiter — Architecture & Fundamentals
A fundamental RTL block for resource sharing and priority resolution.

Clock Domain Crossing — Architecture & Fundamentals
CDC as a core RTL discipline for safe signal transfer

FSM — Architecture & Fundamentals
The core RTL structure for sequencing, control, and protocol logic.

8b/10b — Overview, Tables & Implementation Notes
A combinational encoding/decoding block with running disparity.