Building Blocks
The fundamental functions behind every digital system.
The complete collection of reusable RTL blocks, simulation models, and supporting technical material is maintained in the DexterLab Library. You can access it here: DexterLab Library.
Introduction
Every digital system — from a simple peripheral interface to a high‑speed serial link — is built from a small set of fundamental functions. These functions are the building blocks of digital design.
They appear everywhere:
- in serializers and deserializers
- in protocol encoders
- in arbitration logic
- in clock‑domain crossing
- in data recovery
- in framing and tagging
- in error detection and correction
If you understand the building blocks, you can understand — and design — any architecture.
This page introduces the concept and explains how DexterLab organizes and presents them.
Why Building Blocks Matter
Complex systems are just combinations of simple functions.
A system architect does not start from the system. They start from the functions that make the system possible.
Building blocks matter because:
- they are universal
- they are reusable
- they reduce complexity
- they make architectures predictable
- they allow you to reason at the right level of abstraction
- they let you recognize patterns across different standards
Once you know the blocks, new protocols stop being intimidating. You simply map the specification onto functions you already understand.
Categories of Building Blocks
DexterLab organizes building blocks into a few clear categories.
A) Data Transformation
- Parallel‑to‑Serial (placeholder)
- Serial‑to‑Parallel (placeholder)
- Encoding (8b/10b, scrambling, framing)
- Decoding (placeholder)
B) Control & Arbitration
- Arbiters (round‑robin, priority‑based)
- Flow control
- Tagging and routing (placeholder)
- State machines
C) Timing & Synchronization
- Clock‑domain crossing (CDC)
- FIFOs
- Elastic buffers
- Retiming
D) Clock & Data Recovery
- Correlators (bang‑bang, early‑late, phase aligner)
- PLL‑based recovery
- Oversampling strategies (placeholder)
E) Error Handling
- CRC
- Parity (placeholder)
- Error counters (placeholder)
- Alignment markers (placeholder)
Each category will have dedicated pages with:
- explanation
- architecture
- implementation notes
- RTL fragments
- waveforms
- corner cases
- trade‑offs
How Building Blocks Will Be Presented
Each block will have its own dedicated page with:
- a clear definition
- when and why it is used
- a block diagram
- implementation notes
- RTL fragments (not full files)
- simulation waveforms
- typical pitfalls
- design trade‑offs
- links to architectures that use it
This creates a knowledge graph: Mindset → Blocks → Arch → RTL → Paths
How to Use This Section
This section is designed to be:
- a reference
- a learning path
- a toolbox
- a bridge between theory and practice
If you are new to digital design, start here. If you are studying a new protocol, come back here. If you are designing a new block, compare it with the existing ones.
A Living Library
This section will grow over time.
New blocks will be added as needed, especially when:
- a new architecture requires them
- a case study introduces them
- a protocol highlights a specific function
- a design pattern becomes relevant
The goal is simple: to build a complete, reusable library of the fundamental functions behind every digital system.
Available Building Blocks
Clocking & Synchronization — Overview
Architectural principles and techniques for generating, distributing, aligning, and recovering clocks in FPGA and ASIC systems.
Child pages:
- Clock Generation & Phase Alignment — Architecture & Fundamentals
- Clock Trees — Architecture & Practical Considerations
- Clock Domain Crossing — Architecture & Fundamentals
- Clock Domain Crossing — Practical Guidelines
- Clock & Data Recovery — Overview & Families
- Clock Recovery — Architecture & Fundamentals
Control & Data Path — Overview
Foundational elements for coordinating data movement, managing shared resources, and structuring digital pipelines.
Child pages:
- FIFO — Architecture & Fundamentals
- Arbiter — Architecture & Fundamentals
- FSM — Architecture & Fundamentals
- Flow Control — Architecture & Fundamentals
- Pipelining — Architecture & Fundamentals
Timing & Synchronization — Overview
Foundational principles and mechanisms for timing correctness, synchronization, and safe data movement across domains.
Child pages:
- Timing and Synchronization — Principles and Constraints
- Clock Domain Crossing — Architecture & Fundamentals
- Clock Domain Crossing — Practical Guidelines
- FIFO — Architecture & Fundamentals
- Elastic Buffers — Architecture & Practical Considerations
- Retiming — Principles and Techniques (placeholder)
Peripheral Interfaces — Overview
Local serial interfaces for sensors, actuators, PMICs, and embedded devices.
Child pages:
- I²C — Architecture, Framing & Use Cases
- SPI — Architecture, Modes & Timing
- UART — Framing, Flow Control & Use Cases
- I3C — Architecture & Dynamic Addressing
- 1‑Wire — Framing & Low‑Cost Sensor Networks
- MDIO — PHY Management Interface (Referenced Only)
- SMBus / PMBus — Power & System Management (Referenced Only)
Digital Audio Interfaces — Overview
Synchronous and multi‑channel audio transport for automotive and embedded systems.
Child pages:
- I²S — Serial Audio Interface
- TDM — Time‑Division Multiplexed Audio
- PDM — Pulse‑Density Modulation for Digital Microphones
- SoundWire (MIPI) — Architecture & Audio Transport
- SlimBus — Audio/Data Bus for Mobile Systems
- A2B — Automotive Audio Bus
Line Coding — Overview & Families
Conceptual overview of transition‑based, multilevel, block‑coded, and scrambled line‑coding techniques.
Child pages:
- NRZ / NRZI Coding
- Manchester Coding
- Differential Manchester Coding (DME)
- MLT‑3 Coding
- 8b/10b — Overview, Tables & Implementation Notes
- 64b/66b Encoding — Architecture & Fundamentals
- 128b/130b Encoding — Architecture & Fundamentals
- Scrambling — Architecture, Modes & Implementation Notes
- LFSR / PRBS — Overview, Families & Architecture
Data Integrity — Overview
Architectural and mathematical foundations for ensuring data correctness in digital systems.
Child pages:
- CRC — Overview, Families & Architecture
- LFSR / PRBS — Overview, Families & Architecture (shared with Line Coding)
Signal Processing & Synchronization — Overview
Digital techniques for timing recovery, correlation, spreading, and phase tracking.
Child pages:
- Spread Spectrum — Fundamentals
- Spread Spectrum — Implementation Techniques
- Correlator — Architecture & Fundamentals
- Data Recovery / Phase Tracking — Architecture & Fundamentals
Randomness & Entropy — Overview
Architectures and principles behind true random number generation and entropy extraction.
Child pages:
- True Random Number Generators — Architecture & Fundamentals
