Physical Layer — Overview
Introduction
The Physical Layer defines how bits are transmitted across real physical media such as PCB traces, cables, connectors, and differential pairs. It includes both the digital interfaces that connect MAC logic to the PHY and the electrical signaling used by the PHY to drive and receive signals on the physical medium.
This layer bridges the gap between digital protocol logic and the analog world, ensuring that data can be transmitted reliably under real‑world electrical, timing, and channel conditions.
Role of the Physical Layer
The Physical Layer determines:
- how digital data is encoded into electrical signals
- how signals propagate through copper channels
- how receivers recover timing and data
- how noise, attenuation, and reflections affect communication
- how equalization and filtering compensate for channel impairments
- how MAC logic interacts with the PHY through standardized interfaces
It is the foundation of every communication system, from low‑speed single‑ended buses to multi‑gigabit SerDes links.
Structure of This Section
The Physical Layer is organized into two complementary domains:
1. Physical Layer Interfaces — Overview
Digital MAC‑to‑PHY interfaces that define how the MAC exchanges data, control, and management information with the PHY.
Includes:
- MII
- RMII
- GMII
- SGMII
- T1S 3‑Pin MAC‑to‑PMD Interface
These interfaces describe the digital protocol boundary between logic and the physical transceiver.
2. Electrical Signaling & PHY Interfaces — Overview
Electrical and analog aspects of the PHY, including signaling standards, driver architectures, equalization, jitter, and channel modeling.
Includes:
- PMD (10BASE‑T1S electrical)
- LVDS
- SLVS‑EC
- CML
- Voltage‑mode and current‑mode drivers
- PAM‑2 / PAM‑4
- Equalization (CTLE, DFE, FFE)
- Jitter and eye diagrams
- S‑parameters and channel modeling
These topics describe the physical behavior of signals on the medium.
How to Use This Section
Use this section when designing or analyzing:
- Ethernet PHYs (10BASE‑T1S, 100BASE‑T1, 1000BASE‑T1, 10GBASE‑KR)
- high‑speed SerDes links (PCIe, SATA, MIPI, JESD204)
- automotive PHYs and sensor links
- custom differential interfaces
- signal integrity and compliance test setups
This section provides the conceptual and practical foundation for understanding how digital data becomes physical signals and how those signals are recovered reliably.
Summary
The Physical Layer connects digital logic to the real world.
This section provides a unified framework for understanding both the digital MAC‑to‑PHY interfaces and the electrical signaling used by PHYs, enabling robust and scalable physical‑layer design across a wide range of technologies.
