Skid Buffers — Architecture & Implementation Notes

Overview

A skid buffer is a two‑entry elastic buffer designed to break long combinational ready paths while preserving full throughput in valid/ready pipelines. It provides one cycle of elasticity without introducing bubbles, enabling high‑frequency timing closure in deep or wide datapaths.
Skid buffers are widely used in AXI‑Stream interfaces, NoC routers, DSP pipelines, and any system where backpressure must be registered without sacrificing performance.

A skid buffer guarantees:

• full throughput (1 word/cycle)
• no bubble injection
• registered ready path
• bounded backpressure propagation
• deterministic 0–1 cycle latency

1. Why Skid Buffers Are Needed

Modern pipelines often suffer from:

• long combinational ready paths
• high fan‑out on ready signals
• variable‑latency blocks that stall unpredictably
• timing violations on backpressure paths
• bubble injection when ready is registered

Registering the ready signal solves timing issues but introduces bubbles.
Skid buffers eliminate these bubbles by storing one extra word during stalls.

They are essential when:

• Fmax is limited by ready‑path timing
• backpressure must be registered
• throughput must remain 100%
• pipeline stages must be decoupled cleanly

2. Architectural Principles

A skid buffer consists of:

• primary register (pipeline register)
• skid register (extra storage for stalled cycles)
• bypass path (zero‑latency forwarding when empty)
• registered ready path (timing closure)

Operating modes

• Bypass mode: no data stored, data flows directly
• Skid mode: downstream stalls, data is captured in the skid register
• Drain mode: downstream resumes, skid register drains first

Key properties

• no bubbles even with registered ready
• 1‑cycle elasticity
• deterministic behavior
• safe for deep pipelines
• compatible with any valid/ready interface

3. Skid Buffer vs Elastic Buffer

Skid buffers are a specialized form of elastic buffer optimized for timing closure.

Skid buffers are the preferred solution when timing closure is the primary concern.

4. Flow‑Control Behavior

Skid buffers integrate tightly with valid/ready flow control.

Upstream behavior

• ready is registered → no long combinational paths
• backpressure propagates one cycle later
• no data loss because the skid register absorbs the extra word

Downstream behavior

• when downstream stalls, the next word is stored
• when downstream resumes, the stored word is delivered first
• no bubbles appear at the output

Throughput guarantee

If both sides are ready every cycle:

• throughput = 1 word/cycle
• latency = 0 cycles (bypass mode)

If downstream stalls:

• throughput remains 1 word/cycle after stall
• latency increases to 1 cycle only during drain

5. Implementation Styles

1. Classic 2‑Register Skid Buffer

The canonical implementation:

• reg_data: primary pipeline register
• reg_skid: skid register
• valid_data, valid_skid flags
• registered ready path

This is the most widely used version in AXI‑Stream.

2. Distributed Skid Buffers

Multiple skid buffers placed across a pipeline:

• break long ready paths
• reduce fan‑out
• isolate slow blocks
• improve retiming flexibility

Used in:

• DSP pipelines
• multi‑stage arithmetic units
• packet processing pipelines

3. Wide Skid Buffers

For wide datapaths (256–1024 bits):

• registers are replicated
• ready path is still registered
• bypass logic must be optimized

Used in:

• PCIe/USB4 datapaths
• high‑bandwidth NoC routers

6. Practical Considerations

Timing Closure

Skid buffers are one of the most effective tools for:

• breaking long ready paths
• reducing combinational fan‑out
• isolating slow functional blocks
• enabling retiming across pipeline boundaries

Bubble Prevention

Without skid buffers:

• registered ready introduces bubbles
  With skid buffers:
• bubbles are eliminated
• throughput remains 100%

Variable‑Latency Blocks

Skid buffers absorb single‑cycle stalls from:

• multipliers
• dividers
• arbiters
• memory accesses

Placement Guidelines

Place skid buffers:

• at pipeline boundaries
• before/after variable‑latency blocks
• before wide multiplexers
• after deep combinational logic

CDC Boundaries

Skid buffers are not used for clock‑domain crossing.
Use asynchronous FIFOs instead.

7. Use Cases

Skid buffers appear in:

• AXI‑Stream interfaces
• NoC routers
• DSP pipelines
• packet processing engines
• multi‑stage arithmetic units
• high‑frequency datapaths
• pipelines with registered ready paths

They are one of the most important micro‑architectural primitives in modern digital design.

Related Pages

• Elastic Buffers — Architecture & Practical Considerations
  General‑purpose micro‑elasticity structures used to absorb short‑term stalls.
• Flow Control — Architecture & Fundamentals
  Core mechanisms for managing data movement and backpressure.
• Data Path — Architecture & Fundamentals
  Structural principles for building high‑throughput pipelines.
• FIFO — Architecture & Fundamentals
  Elastic buffering and rate matching for larger systems.
• Pipelining — Architecture & Fundamentals
  Stage balancing, retiming, and throughput optimization.

Summary

Skid buffers are two‑entry elastic buffers designed to break long ready paths while preserving full throughput in valid/ready pipelines. They eliminate bubble injection, provide deterministic 0–1 cycle latency, and enable high‑frequency timing closure in deep or wide datapaths.

As a specialized form of elastic buffer, they are essential in AXI‑Stream interfaces, DSP pipelines, NoC routers, and any system requiring robust, high‑performance flow control.