Clock & Data Recovery – Overview & Families

Overview

This page introduces the timing‑recovery mechanisms used in embedded‑clock and source‑synchronous interfaces, and classifies the main architectural families used in modern digital communication systems.

Clock & Data Recovery (CDR) encompasses the techniques used to reconstruct timing information from a serial data stream or to align a forwarded clock to the center of the data eye.

Modern digital interfaces fall into two categories:

• Embedded‑clock interfaces — the clock is not transmitted; the receiver must recover it from data transitions.
• Source‑synchronous interfaces — the transmitter forwards a clock; the receiver must align it to the data.

Both require robust timing extraction, jitter tolerance, and continuous tracking of drift, skew, and channel distortions.
This page introduces the architectural families, the operating principles, and the protocol‑level use cases.

1. Embedded‑Clock Interfaces

In embedded‑clock systems, the receiver must reconstruct the sampling clock directly from the data stream.
Examples include:

• PCIe
• SATA
• USB3
• DisplayPort
• Ethernet (100BASE‑X, 1000BASE‑X)
• custom SERDES

These systems rely on:

• transition‑based timing extraction
• phase detectors (bang‑bang, Gardner, Mueller & Müller)
• loop filters
• controlled oscillators (VCO, DCO, phase interpolators)
• oversampling or delay‑line loops

Embedded‑clock CDR must handle jitter, wander, frequency offsets, and channel dispersion.

2. Source‑Synchronous Interfaces

In source‑synchronous systems, the transmitter forwards a clock along with data.
Examples include:

• MIPI D‑PHY
• JESD204B
• DDR / LPDDR
• custom forwarded‑clock links

The receiver must:

• align the forwarded clock to the center of the data eye
• compensate skew and drift
• track PVT variations
• maintain deterministic timing relationships

Phase alignment uses:

• delay‑line sampling
• multi‑tap correlators
• pattern‑based alignment
• eye‑center detectors
• training sequences or dynamic tracking

3. Architectural Families

Embedded‑Clock CDR Families

• Bang‑Bang CDR (Alexander, Hogge) — binary early/late decisions
• Mueller & Müller (decision‑directed) — symbol‑based timing estimation
• Gardner (non‑data‑aided) — mid‑symbol timing error
• Oversampling CDR — multiple sampling phases, digital selection
• Digital delay‑line CDR — synthesizable, portable, crystal‑less operation

Source‑Synchronous Alignment Families

• Delay‑line sampling — multi‑tap data sampling
• Edge‑based correlators — transition‑based eye‑center detection
• Pattern‑based alignment — training sequences
• Eye‑center detectors — histogram‑based phase selection

4. Timing Metrics

Both CDR and phase‑alignment systems rely on quantitative metrics:

• transition density
• early/late symmetry
• bit stability
• pattern‑match score
• edge histograms
• drift and skew measurements

These metrics guide sampling‑point selection and loop convergence.

5. Use Cases Across Modern Protocols

High‑Speed SERDES

Embedded‑clock CDR with bang‑bang or Mueller & Müller detectors, phase interpolators, and equalization.

Ethernet PHYs

Digital CDR loops, oversampling receivers, and delay‑line‑based timing extraction.

MIPI / JESD204B

Forwarded‑clock alignment using delay lines, correlators, and training sequences.

DDR / LPDDR

Read‑leveling and write‑leveling using multi‑tap sampling and eye‑center detection.

Crystal‑less Systems

Digital delay‑line CDR compensating ±5% oscillator error (your eSYNC architecture).

Related Pages

• Clock Recovery — Architecture & Fundamentals
  Core timing‑recovery algorithms for embedded‑clock interfaces, including bang‑bang detectors, oversampling loops, and digital delay‑line architectures.
• Clock Generation & Phase Alignment — Architecture & Fundamentals
  Forwarded‑clock alignment techniques using delay lines, correlators, eye‑center detection, and dynamic skew compensation.
• Correlator — Architecture & Fundamentals
  Digital correlation engines used for edge detection, pattern matching, and timing estimation in CDR and source‑synchronous receivers.
• Clock Trees — Architecture & Practical Considerations
  Clock‑distribution strategies that influence jitter, skew, and timing margins in systems using CDR or forwarded‑clock alignment.

Summary

Clock & Data Recovery unifies the timing‑extraction mechanisms used in embedded‑clock and source‑synchronous interfaces.
Embedded‑clock CDR reconstructs the sampling clock from data transitions; source‑synchronous alignment centers the forwarded clock within the data eye.
Both rely on transition‑based metrics, delay‑line sampling, correlation engines, and robust loop architectures.
These techniques form the foundation of modern SERDES, Ethernet PHYs, DDR interfaces, and high‑speed digital communication systems.

Together with phase alignment, CDC, and clock‑generation techniques, CDR forms one of the core pillars of the Clocking & Synchronization domain.