Glossary
The Glossary collects essential definitions used across digital design, microelectronics, and system architecture. Each entry is short, precise, and focused on the meaning that matters in engineering practice.
The goal is to remove ambiguity: many technical terms are used differently in different contexts, and the glossary provides a stable reference for the terminology used in Dexter’s Laboratory.
Entries are added progressively, following the needs of the learning paths and the technical notes.
Index
A · B · C · D · E · F · G · H · I · J · K · L · M · N · O · P · Q · R · S · T · U · V · W · X · Y · Z
A
AXI4
Category: Protocol
Definition: High‑performance, memory‑mapped bus protocol with independent read/write channels and burst support.
Context: Core interconnect in many DexterLab architectures.
AXI4‑Lite
Category: Protocol
Definition: Simplified AXI4 subset for low‑bandwidth register access.
Context: Used for control/status paths.
APB
Category: Protocol
Definition: Simple, low‑bandwidth bus for register access and peripheral control.
Context: Used for configuration registers.
Arbiter
Category: Architecture
Definition: Logic that selects one requester among multiple contenders.
Context: Used in bus interconnects.
Address Decoder
Category: Architecture
Definition: Logic that maps address ranges to specific slaves or memory regions.
Context: Used in interconnects and memory subsystems.
B
Backpressure
Category: Protocol
Definition: Mechanism where a receiver slows or stops a sender.
Context: Implemented via ready/valid.
Burst Transfer
Category: Protocol
Definition: Sequence of consecutive data beats under one address phase.
Context: AXI4 supports multiple burst types.
Bus Matrix
Category: Architecture
Definition: Interconnect allowing multiple masters to access multiple slaves concurrently.
Context: Used in complex SoCs.
Byte Enable
Category: Protocol
Definition: Signals indicating which bytes of a word are valid.
Context: Used in memory‑mapped interfaces.
C
CDC (Clock Domain Crossing)
Category: Timing
Definition: Safe transfer of signals between different clock domains.
Context: Critical to avoid metastability.
Clock Gating
Category: Power
Definition: Technique to disable clocks to inactive logic.
Context: Used in low‑power SoCs.
Clock Skew
Category: Timing
Definition: Difference in arrival time of the same clock edge.
Context: Impacts setup/hold margins.
Combinational Logic
Category: RTL
Definition: Logic whose outputs depend only on current inputs.
Context: Basis of datapaths.
CSR (Control and Status Register)
Category: Architecture
Definition: Register used to configure hardware blocks.
Context: Exposed via APB or AXI4‑Lite.
Clock Domain
Category: Timing
Definition: Region of logic driven by the same clock.
Context: CDC occurs between domains.
Configuration Register
Category: Architecture
Definition: Register used to program operating modes.
Context: Accessed via APB or AXI4‑Lite.
D
DMA (Direct Memory Access)
Category: Architecture
Definition: Engine that moves data without CPU intervention.
Context: Essential for high‑bandwidth pipelines.
Debounce
Category: RTL
Definition: Filtering technique for noisy inputs.
Context: Used for buttons and interrupts.
Duty Cycle
Category: Timing
Definition: Ratio of high time to total clock period.
Context: Impacts timing margins.
Data Path
Category: Architecture
Definition: Portion of a design that processes data.
Context: Separated from control logic.
Dual‑Port RAM
Category: Memory
Definition: Memory with two independent access ports.
Context: Used for concurrent access.
E
Edge Triggering
Category: Timing
Definition: Flip‑flop behavior where state changes occur on edges.
Context: Foundation of synchronous design.
Enable Signal
Category: RTL
Definition: Control signal that allows register updates.
Context: Used in pipelines.
Error Flag
Category: RTL
Definition: Signal indicating an error condition.
Context: Exposed via status registers.
Edge Detector
Category: RTL
Definition: Circuit that generates a pulse on input transitions.
Context: Used for control signals.
F
FIFO
Category: RTL
Definition: First‑In First‑Out buffer.
Context: Used in CDC and streaming.
FSM (Finite State Machine)
Category: RTL
Definition: Control logic defined by states and transitions.
Context: Core of many RTL modules.
Fanout
Category: Timing
Definition: Number of loads driven by a signal.
Context: High fanout increases delay.
Flow Control
Category: Protocol
Definition: Mechanisms regulating data transfer rate.
Context: Implemented via backpressure.
Flag Register
Category: RTL
Definition: Register storing status bits.
Context: Used in FIFOs and controllers.
G
Gray Code
Category: Timing
Definition: Encoding where only one bit changes at a time.
Context: Used in async FIFO pointers.
Gating Cell
Category: Power
Definition: Cell implementing safe clock gating.
Context: Prevents glitches.
Glitch
Category: Timing
Definition: Short unwanted pulse caused by unequal delays.
Context: Can cause incorrect sampling.
Global Clock
Category: Clocking
Definition: Clock distributed across large design regions.
Context: Requires skew control.
H
Handshake Protocol
Category: Protocol
Definition: Synchronization via ready/valid or req/ack.
Context: Foundation of many buses.
Hold Time
Category: Timing
Definition: Minimum time input must remain stable after clock edge.
Context: Violations cause metastability.
Hazard
Category: Architecture
Definition: Condition preventing next operation from executing.
Context: Common in pipelines.
High‑Impedance (Hi‑Z)
Category: RTL
Definition: Output state where driver disconnects.
Context: Used in tri‑state buses.
I
IP Core
Category: Architecture
Definition: Reusable hardware block.
Context: DexterLab modules follow IP‑style design.
Interrupt
Category: Architecture
Definition: Event signaling CPU to run a service routine.
Context: Used for asynchronous events.
Instruction Decoder
Category: Architecture
Definition: Logic translating instructions into control signals.
Context: Central in CPUs.
Idle State
Category: Protocol
Definition: State where no valid transfer occurs.
Context: Baseline state in many protocols.
J
Jitter
Category: Timing
Definition: Short‑term variation in clock edge timing.
Context: Impacts PLLs.
JTAG
Category: Test
Definition: Standard test access port and boundary scan.
Context: Used for debug and programming.
L
Latch
Category: RTL
Definition: Level‑sensitive storage element.
Context: Avoided in FPGA flows.
Latency
Category: Architecture
Definition: Time between input and output.
Context: Key metric in pipelines.
Load‑Enable Register
Category: RTL
Definition: Register updating only when enable is asserted.
Context: Used in pipelines.
Logic Cone
Category: RTL
Definition: Set of logic driving a signal.
Context: Important for timing.
M
Metastability
Category: Timing
Definition: Undefined flip‑flop state due to timing violations.
Context: Primary CDC risk.
Mux (Multiplexer)
Category: RTL
Definition: Logic selecting one input among many.
Context: Used in datapaths.
Memory‑Mapped I/O
Category: Architecture
Definition: Peripheral registers accessed via address space.
Context: Used in SoCs.
Multi‑Cycle Path
Category: Timing
Definition: Path allowed to take multiple cycles.
Context: Requires timing constraints.
N
Non‑Blocking Assignment
Category: RTL
Definition: Assignment style where updates occur concurrently.
Context: Used in sequential logic.
Noise Margin
Category: Interface
Definition: Maximum tolerable noise without logic error.
Context: Relevant for I/O.
O
Oscillator
Category: Clocking
Definition: Circuit generating a periodic signal.
Context: Used as clock source.
Overflow
Category: RTL
Definition: Condition where arithmetic result exceeds range.
Context: Used in counters and ALUs.
P
Pipeline
Category: Architecture
Definition: Sequence of stages operating concurrently.
Context: Used in datapaths.
PLL
Category: Clocking
Definition: Circuit generating stable clocks.
Context: Used for frequency synthesis.
Power Gating
Category: Power
Definition: Technique to shut down inactive logic.
Context: Used in low‑power SoCs.
Parity Bit
Category: Error Detection
Definition: Bit used to detect single‑bit errors.
Context: Used in memories.
Port Mapping
Category: RTL
Definition: Association of signals to module ports.
Context: Fundamental in RTL design.
Q
QoS
Category: Protocol
Definition: Mechanisms prioritizing or guaranteeing bandwidth.
Context: AXI4 includes QoS fields.
Quiescent State
Category: Architecture
Definition: Stable state with no activity.
Context: Used in low‑power modes.
R
Reset Synchronizer
Category: Timing
Definition: Circuit safely releasing async reset.
Context: Mandatory in multi‑clock designs.
Round‑Robin Arbiter
Category: Architecture
Definition: Arbiter cycling through requesters fairly.
Context: Used in shared buses.
Read‑Modify‑Write
Category: Architecture
Definition: Read, alter, and write back sequence.
Context: Sensitive to concurrency.
Ready Signal
Category: Protocol
Definition: Indicates receiver can accept data.
Context: Paired with valid.
S
Setup Time
Category: Timing
Definition: Minimum time input must be stable before clock edge.
Context: Violations cause metastability.
Synchronizer
Category: Timing
Definition: Flip‑flop chain reducing metastability probability.
Context: Simplest CDC primitive.
Stall
Category: Architecture
Definition: Temporary halt of pipeline progression.
Context: Used to handle hazards.
State Encoding
Category: RTL
Definition: Binary encoding of FSM states.
Context: Impacts area and speed.
Synchronous Reset
Category: Timing
Definition: Reset applied on clock edge.
Context: Easier to integrate.
T
Throughput
Category: Architecture
Definition: Data processed per unit time.
Context: Key metric in streaming.
Tri‑State Buffer
Category: RTL
Definition: Buffer with high‑impedance state.
Context: Used in shared buses.
Timing Closure
Category: Implementation
Definition: Meeting all timing constraints.
Context: Key step in FPGA/ASIC flows.
Toggle Rate
Category: Power
Definition: Frequency of signal transitions.
Context: Impacts dynamic power.
U
UART
Category: Interface
Definition: Simple serial protocol with start/stop bits.
Context: Used for debug.
Unsigned Integer
Category: RTL
Definition: Integer without sign bit.
Context: Used in counters.
V
Valid Signal
Category: Protocol
Definition: Indicates data on bus is meaningful.
Context: Paired with ready.
Vector
Category: RTL
Definition: Multi‑bit signal.
Context: Used in datapaths.
Verification Environment
Category: Verification
Definition: Infrastructure for verifying a design.
Context: Often built using UVM.
W
Write Strobe
Category: Protocol
Definition: Indicates which byte lanes are written.
Context: Used in AXI4.
Watchdog Timer
Category: Safety
Definition: Timer triggering reset if not serviced.
Context: Used to recover from hangs.
X
X‑Propagation
Category: Verification
Definition: Unknown values propagating in simulation.
Context: Important for reset analysis.
X‑State
Category: Verification
Definition: Unknown logic value in simulation.
Context: Represents uninitialized signals.
Y
Yield
Category: Manufacturing
Definition: Percentage of chips functioning correctly.
Context: Impacts production cost.
Y‑Flip
Category: RTL
Definition: Bitwise inversion of a vector.
Context: Used in data formatting.
Z
Zero‑Latency Path
Category: Architecture
Definition: Output produced in same cycle as input.
Context: Used in combinational datapaths.
Zeroization
Category: Security
Definition: Clearing sensitive data.
Context: Used in secure designs.
