RTL Design Conventions

This page collects the conventions used across DexterLab RTL blocks to ensure consistency, readability, interoperability, and ease of integration across different projects. The guidelines cover naming, reset strategy, clocking assumptions, handshake protocols, and coding style.

Naming Conventions

• Consistent use of snake_case for internal signals and variables.
• Use of CamelCase for modules, entities, and components.
• Standardized suffixes to indicate signal direction and role (_i, _o, _q, _d, _n, etc.).
• Descriptive, unambiguous names for control and handshake signals.

Reset Strategy

• Explicit definition of synchronous or asynchronous reset for each block.
• Clear indication of reset polarity (active‑high or active‑low).
• Reset applied only to registers that require a defined startup state.
• Avoid unnecessary global resets to improve timing closure.

Clocking Assumptions

• A single clock domain per module unless explicitly documented otherwise.
• CDC handled through dedicated synchronizers or FIFOs with integrated crossing logic.
• Clear specification of expected clock frequency and timing constraints.

Handshake Protocols

• Standardized use of ready/valid, req/ack, or equivalent protocols.
• Documented behavior under backpressure conditions.
• No implicit dependency between handshake and reset.
• Defined timing behavior for each interface.

Coding Style

• Consistent guidelines for VHDL and Verilog/SystemVerilog.
• Clear separation between combinational and sequential logic.
• Avoidance of unintended latches.
• Concise but meaningful comments for each functional section.
• Modular, reusable code structure.

Reference Template

For creating new RTL block entries, use the internal reference template:

RTL Block Template

(internal page, not part of the public taxonomy)