MIPI CSI/DSI — Lane Management, Framing & Packetization
Overview
MIPI CSI (Camera Serial Interface) and MIPI DSI (Display Serial Interface) are high‑speed, low‑power serial interfaces widely used in mobile, embedded, and imaging systems. Both rely on the MIPI D‑PHY, C‑PHY, or A‑PHY physical layers and share a common architectural foundation:
- multi‑lane scalable serial links
- structured packetization
- low‑power and high‑speed signaling modes
- lane management and synchronization
- robust framing and error detection
CSI is optimized for unidirectional high‑bandwidth camera data, while DSI is optimized for display command and pixel streaming. Despite their different roles, they share the same packet‑based transport model and lane architecture.
Protocol Architecture
Physical Layer
CSI/DSI operate over:
- D‑PHY (most common):
- high‑speed differential signaling
- low‑power single‑ended signaling
- per‑lane rates up to several Gbps
- C‑PHY:
- 3‑wire trios
- embedded clocking
- higher symbol efficiency
- A‑PHY:
- long‑reach automotive links
- high robustness and EMI tolerance
The PHY layer supports dynamic switching between Low‑Power (LP) and High‑Speed (HS) modes.
Link Layer
The link layer provides:
- lane initialization
- synchronization
- packet framing
- error detection (ECC, CRC)
- escape sequences and control signaling
CSI and DSI share similar link‑layer concepts but differ in packet types and semantics.
Protocol Layer
Defines:
- packet formats
- virtual channels
- pixel or data types
- command modes (DSI)
- frame and line structure (CSI)
This layer is responsible for mapping image or display data into packets.
Lane Management
Multi‑Lane Architecture
CSI/DSI support:
- 1, 2, 3, or 4 data lanes (sometimes more in advanced versions)
- 1 dedicated clock lane (D‑PHY) or embedded clocking (C‑PHY)
Lanes operate in parallel to increase throughput.
Lane Initialization
Initialization includes:
- LP‑11 → LP‑01 → LP‑00 transitions
- HS entry sequences
- clock lane stabilization
- data lane synchronization
These transitions ensure reliable bring‑up.
Lane Skew and Deskew
Because lanes operate independently, skew may occur due to:
- PCB routing differences
- temperature variations
- PHY timing offsets
CSI/DSI include deskew mechanisms to realign lanes at packet boundaries.
Virtual Channels
CSI supports up to 4 virtual channels, enabling:
- multiple cameras on the same link
- metadata and image data separation
- multi‑stream operation
DSI uses virtual channels for multi‑display or command/data separation.
Framing and Packetization
Packet Types
CSI/DSI use two main packet types:
- Short packets — small control messages (header only)
- Long packets — payload‑carrying packets (image data, pixel streams, commands)
Both include:
- 2‑byte header
- 1‑byte ECC
- optional payload
- 2‑byte CRC (long packets only)
CSI Packetization
CSI maps image sensor output into:
- frame start / frame end packets
- line start / line end packets
- long packets containing pixel data
- embedded metadata packets
This structure mirrors the natural hierarchy of image frames.
DSI Packetization
DSI supports two modes:
- Command Mode — register writes, configuration commands
- Video Mode — continuous pixel streaming
Video mode uses:
- sync packets
- blanking packets
- pixel data packets
DSI packetization is optimized for display timing requirements.
Low‑Power vs High‑Speed Modes
Low‑Power (LP) Mode
Used for:
- control commands
- initialization
- low‑bandwidth transfers
- power‑sensitive operations
LP mode uses single‑ended signaling and supports bidirectional communication.
High‑Speed (HS) Mode
Used for:
- pixel data
- image data
- high‑bandwidth streaming
HS mode uses differential signaling with embedded clocking (C‑PHY) or a dedicated clock lane (D‑PHY).
Switching between LP and HS is part of the protocol’s state machine.
Error Detection and Reliability
ECC (Header Protection)
The 1‑byte ECC protects:
- data type
- virtual channel
- word count
Single‑bit errors can be corrected; multi‑bit errors detected.
CRC (Payload Protection)
Long packets include a 16‑bit CRC covering the payload.
Escape Mode
Escape sequences allow:
- error recovery
- low‑power entry
- special signaling
- bidirectional communication (LP mode)
Synchronization Errors
Loss of synchronization triggers:
- lane reset
- re‑entry into LP mode
- reinitialization sequences
Performance Considerations
Throughput
Throughput depends on:
- number of lanes
- per‑lane rate
- encoding efficiency (C‑PHY vs D‑PHY)
CSI‑2 and DSI‑2 significantly increase bandwidth over earlier versions.
Latency
CSI/DSI provide low, deterministic latency suitable for:
- real‑time imaging
- AR/VR
- automotive cameras
Power Efficiency
LP/HS switching enables:
- low idle power
- efficient control signaling
- reduced thermal load
Scalability
CSI/DSI scale across:
- mobile devices
- embedded systems
- automotive cameras
- high‑resolution displays
Use Cases
CSI
- smartphone and tablet cameras
- automotive radar sensors (short‑range, mid‑range, long‑range)
- automotive ADAS cameras
- industrial vision sensors
- drones and robotics
- multi‑camera systems
DSI
- smartphone and tablet displays
- VR/AR headsets
- automotive instrument clusters
- embedded displays
- high‑resolution panels
Comparison of CSI and DSI
| Feature | CSI | DSI |
|---|---|---|
| Direction | Sensor → Host | Host → Display |
| Packet Types | Image frames, metadata | Commands, pixel streams |
| Virtual Channels | Yes | Yes |
| Modes | HS + LP | HS + LP |
| Use Case | Cameras, Radar | Displays |
Related Pages
- SERDES & High‑Speed Interfaces — Architecture
- Packetization — Architecture & Data Flow
- Reassembly & Segmentation — Architecture & Use Cases
- JESD204 — Transport Layer, Framing & Lane Alignment
Summary
MIPI CSI and DSI provide scalable, low‑power, high‑bandwidth serial interfaces for cameras and displays. Through multi‑lane architectures, structured packetization, LP/HS signaling, and robust error detection, they deliver efficient and deterministic data transport across mobile, embedded, and automotive systems. Their shared architecture makes them ideal case studies for packet‑based serial protocols.
