DexterLab

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Home

Introduction to the Lab and direct access to the main sections.

Theory

Concepts, principles, and foundational knowledge for digital and system architecture.
(Content under construction.)

Design Library

Reusable RTL blocks, implementation notes, models, and technical building blocks.
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Lab Overview

Technical map of the site and high‑level structure of all domains.

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Safety

Safety Architecture

  • Safety Architecture as an Early Design Phase
  • ASIL, SEooC, and FIT Metrics in Functional Safety
  • Functional Safe States and Fault Reaction Strategies
  • Watchdog and Safe State Management
  • Fault Collection and Control Unit (FCCU)
  • Board‑Level Fault Signaling

Safety in Power / Reset / Clocking

  • Safety in Power Management
  • Safety in Reset
  • Safety in Clocking

Safety Diagnostics & Mechanisms

  • ECC and Memory Protection
  • CRC and Data Integrity
  • BIST and Self‑Test Strategies
  • Peripheral Diagnostics
  • Sensor Plausibility and Redundancy
  • Actuator Diagnostics and Degradation Modes

Safety Integration on Board

  • PMIC ↔ MCU Fault Coordination
  • External Watchdog Integration
  • Power‑Good, Reset‑Good, Safe‑State Lines

Safety Lifecycle & Documentation

  • Safety Manual
  • FMEDA and FIT Budgeting
  • Safety Requirements and Traceability
  • Verification & Validation
  • Safety Case and Compliance

Security

Security Architecture

  • Security in System Architecture
  • Threat Modeling and Attack Surfaces
  • Security vs Safety Interactions

Security in Hardware Blocks

  • Security in Data Path & Buffers
  • Security in Reset
  • Security in Power Management
  • Security in PHY Interfaces
  • Anti‑Tamper and Fault Injection Protection

Cryptography & Trust Anchors

  • Secure Boot and Key Management
  • Hardware Security Modules and PUFs
  • Cryptographic Keys, Provisioning, and Device Lifecycle
  • Lifecycle and Provisioning Security
  • Random Number Generation and Entropy Sources
  • Data Integrity — CRC, MAC, and Digital Signatures

Firmware & Software Security

  • Firmware Update and Recovery Mechanisms
  • Secure Debug and Access Control
  • Secure Communication Protocols
  • Memory Protection and Isolation

Security Lifecycle

  • Manufacturing → OEM → User → FAR → End‑of‑Life
  • Secure Provisioning
  • Key Rotation and Revocation
  • Secure Logging and Audit Trails

Cross‑Domain (Safety + Security)

Shared Mechanisms

  • Fault Injection Protection
  • Tamper Detection
  • Secure Boot protecting Safety Configuration
  • Lifecycle States protecting FCCU and Watchdog Configuration
  • Board‑Level Fault Lines Protection

Shared Architecture

  • Early‑Phase Design
  • Redundancy and Diversity
  • Diagnostic Coverage
  • Safe‑State Enforcement
  • Trust Anchors and Configuration Locking

Shared Documentation

  • Safety Manual
  • Security Manual
  • FMEDA with Security‑Aware FIT Considerations
  • Threat Model
  • Combined Safety & Security Case