🛠️ Design Library — Build, Simulate, and Reuse
The spirit of this section
The Design Library is the workbench of the Lab — the place where ideas turn into circuits, where concepts become modules, and where you can build something real with your own hands. It’s the practical corner of that underground workshop we all imagined as kids: quiet, focused, full of tools you can pick up and use right away.
Here, you don’t just understand how things work — you make them work.
What you’ll find here
The Design Library contains reusable building blocks for real digital systems. Everything is designed to be clear, synthesizable, and ready to integrate.
- RTL modules — clean, readable, reusable
- Testbenches — to simulate and validate behavior
- Integration notes — how to connect blocks in real designs
- Reference models — when behavior needs to be checked or compared
- Implementation details — timing, constraints, corner cases
Each block is built with the same philosophy: clarity, reusability, and engineering discipline.
Who this section is for
The Design Library is for anyone who wants to build:
- Students who want to see real, working RTL
- Young professionals who need reliable blocks for projects
- Experienced engineers who want clean modules to integrate
- Makers and explorers who enjoy building things from scratch
If you’ve ever thought “I wish I had a clean block for this”, this is your place.
How to use this section
You can approach the Design Library in two ways:
- Pick a block and use it — copy, adapt, integrate
- Study the implementation — understand the architecture behind it
Every module is documented with intent, behavior, and integration notes, so you always know what you’re using and why it works.
Where to begin
As the Library grows, you’ll find categories like:
- Communication interfaces
- Timing and clocking blocks
- Control logic and state machines
- Data paths and processing elements
- Utility modules (arbiters, FIFOs, encoders, decoders)
For now, think of this page as your entry point — the door to the practical side of DexterLab.
A place to build with confidence
The Design Library is here to help you create real digital systems with clarity and reliability. Take your time. Explore the blocks. Reuse what you need. This is the part of the Lab where ideas become hardware.
🔧 Release Levels & Structure
To keep the Design Library coherent, scalable, and easy to navigate, every release follows a clear structure. Each design belongs to one of three release levels.
Level 1 — RTL Block (Atomic Building Block)
A single, synthesizable hardware module with a clean interface and minimal dependencies.
Includes:
/rtl/— synthesizable RTL/tb/— self‑contained testbench/sim/— simulation scripts/docs/— short architectural notes/examples/— integration snippetsREADME.md— intent, parameters, timing notesLICENSE- optional CI (lint + basic simulation)
Examples: FIFO, Arbiter, CRC Engine, LFSR, Synchronizer.
This is the foundation of the Library — small, reusable, disciplined.
Level 2 — Architecture Module (Composed Subsystem)
A complete architecture built from multiple RTL blocks, reference models, and a structured verification environment.
Includes:
- multiple RTL blocks (master, slave, datapath, control)
- behavioral models for verification
- hierarchical testbench
- stimulus files and expected outputs
- protocol checkers or sniffers
- documentation of architecture and behavior
- integration notes
- optional FPGA constraints and synthesis scripts
- CI with regression tests
Examples: SPI Interface, Packet Parser Pipeline, DMA Engine, AXI4‑Stream Switch.
Level 3 — Reference Design (Complete System)
A full, documented system intended as a learning platform or integration example.
Includes:
- full architecture documentation
- RTL + behavioral models
- complete verification environment
- datasets, logs, and analysis tools
- FPGA build flow
- performance metrics
- integration guide
- release notes and roadmap
Examples: MacSec Engine, Radar Post‑Processing Pipeline, Secure Boot Reference.
📁 Repository Structure & Local Copy
Every release in the Design Library has:
- a GitHub repository (public, versioned)
- a local working copy
- a link from the DexterLab page
- a consistent folder structure
- a README aligned with the site page
This ensures that documentation, repository, and workspace always reflect the same design image.
🔤 Naming & Versioning
- Repository names follow:
dexterlab-<design-name> - Releases use semantic versioning:
v1.0.0,v1.1.0,v2.0.0 - Each release includes:
- changelog
- known issues
- roadmap
🔗 Linking to the Design Library
Every theoretical page (e.g., SPI Interface — Architecture & Modes) links to the corresponding GitHub release:
See also: SPI Interface — Design Library Release (GitHub repository link)
This keeps theory and implementation tightly connected.
🎯 Why this structure matters
This framework ensures that:
- every release is complete
- nothing is forgotten
- the Library grows without chaos
- users always know what to expect
- you can scale from small blocks to full systems
- SPI, I²C, UART, and future interfaces fit naturally
This is the foundation of the DexterLab Design Library.
📦 Published RTL Blocks (Updated October 2026)
RTL Design Conventions
Guidelines for naming, reset, clocking, handshake, and coding style.
AXI4‑Stream FIFO
Reusable FIFO for AXI4‑Stream pipelines. Supports backpressure, configurable depth, and high‑frequency timing closure.
AXI4‑Stream FIFO — Source & Simulation
Complete RTL, testbench, waveforms, and integration notes.
CRC — RTL Architecture & Implementation Notes
Design considerations for CRC engines, including LFSR architectures and pipelining.
PMD — 10BASE‑T1S Electrical Interface
Electrical characteristics of the 10BASE‑T1S physical medium attachment.
🔵 DexterLab Command Parser — Latest Release: v1.1.0
A fully documented and stable command parser that translates high‑level .cmd files into structured bus operations compatible with AXI‑FULL, AXI‑LITE, AHB‑FULL, and AHB‑LITE interfaces.
👉 Learn more → DexterLab Command Parser
👉 GitHub → https://github.com/dexterlab-io/parser
Status: Stable Version: 1.1.0 Release Date: 8 October 2026
🔵 DexterLab Parser — AXI‑Full Edition — Latest Release: v1.1.0
Complete AXI‑FULL backend supporting multi‑beat bursts, full handshake compliance, and byte‑enable propagation.
👉 Learn more → DexterLab Command Parser AXI‑Full Edition
👉 GitHub → https://github.com/dexterlab-io/parser_axi_full
Status: Stable Version: 1.1.0 Release Date: 8 October 2026
🔵 DexterLab Parser — AXI‑Lite Edition — Latest Release: v1.0.0
Complete AXI‑Lite backend supporting single‑beat read/write operations, AXI‑Lite handshake logic, and structured response mapping.
👉 Learn more → DexterLab Command Parser AXI‑Lite Edition
👉 GitHub → https://github.com/dexterlab-io/parser_axi_lite
Status: Stable Version: 1.0.0 Release Date: 8 October 2026
